Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Inverter Inverter 74VHCT SO 14

1. General description

The 74VHC14; 74VHCT14 are a high-speed Si-gate CMOS devices and are pin

compatible with Low-power Schottky TTL (LSTTL). They are speciﬁed in compliance with

JEDEC standard No. 7A.

The 74VHC14; 74VHCT14 provide six inverting buffers with Schmitt-trigger action. They

are capable of transforming slowly changing input signals into sharply deﬁned, jitter-free

output signals.

2. Features

n Balanced propagation delays

n All inputs have Schmitt-trigger action

n Inputs accept voltages higher than V

n Input levels:

u The 74VHC14 operates with CMOS input level

u The 74VHCT14 operates with TTL input level

n ESD protection:

u HBM EIA/JESD22-A114E exceeds 2000 V

u MM EIA/JESD22-A115-A exceeds 200 V

u CDM EIA/JESD22-C101C exceeds 1000 V

n Multiple package options

n Speciﬁed from −40 °C to +85 °C and from −40 °C to +125 °C

74VHC14; 74VHCT14

Hex inverting Schmitt trigger

Rev. 01 — 17 August 2009 Product data sheet

Summary of content (16 pages)

PAGE 1
74VHC14; 74VHCT14 Hex inverting Schmitt trigger Rev. 01 — 17 August 2009 Product data sheet 1. General description The 74VHC14; 74VHCT14 are a high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74VHC14; 74VHCT14 provide six inverting buffers with Schmitt-trigger action. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. 2.
PAGE 2
74VHC14; 74VHCT14 NXP Semiconductors Hex inverting Schmitt trigger 3. Ordering information Table 1. Ordering information Type number Package 74VHC14D Temperature range Name Description Version −40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.
PAGE 3
74VHC14; 74VHCT14 NXP Semiconductors Hex inverting Schmitt trigger 5. Pinning information 5.1 Pinning 1 1A terminal 1 index area 74VHC14 74VHCT14 14 VCC 74VHC14 74VHCT14 1Y 2 13 6A 1A 1 14 VCC 2A 3 12 6Y 1Y 2 13 6A 2Y 4 11 5A 2A 3 12 6Y 3A 5 2Y 4 11 5A 3Y 6 6 9 4A 7 8 4Y 8 3Y GND 10 5Y 9 4Y 10 5Y 7 5 GND 3A GND(1) 4A 001aak043 Transparent top view 001aak042 (1) The die substrate is attached to this pad using conductive die attach material.
PAGE 4
74VHC14; 74VHCT14 NXP Semiconductors Hex inverting Schmitt trigger 6. Functional description Table 3. Function table[1] Input Output nA nY L H H L [1] H = HIGH voltage level; L = LOW voltage level. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage VI input voltage Conditions Min Max Unit −0.5 +7.0 V −0.5 +7.
PAGE 5
74VHC14; 74VHCT14 NXP Semiconductors Hex inverting Schmitt trigger 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max IO = −50 µA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = −50 µA; VCC = 3.0 V 2.9 3.0 - 2.9 - 2.9 - V IO = −50 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = −4.
PAGE 6
74VHC14; 74VHCT14 NXP Semiconductors Hex inverting Schmitt trigger 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7. Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max Min Max CL = 15 pF - 4.3 12.8 1.0 15.0 1.0 16.0 ns CL = 50 pF - 5.8 16.3 1.0 18.0 1.0 20.5 ns - 3.2 8.6 1.0 10.0 1.0 11.0 ns - 4.2 10.6 1.0 12.0 1.0 13.
PAGE 7
4VHC14; 74VHCT14 NXP Semiconductors Hex inverting Schmitt trigger 11. Waveforms VI VM nA input VM GND t PHL t PLH VOH VM nY output VM VOL mna344 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Input to output propagation delays Table 8. Measurement points Type Input Output VM VM 74VHC14 0.5VCC 0.5VCC 74VHCT14 1.5 V 0.
PAGE 8
74VHC14; 74VHCT14 NXP Semiconductors Hex inverting Schmitt trigger Table 9. Test data Type Input Load Test VI tr, tf CL 74VHC14 VCC ≤ 3.0 ns 50 pF, 15 pF tPLH, tPHL 74VHCT14 3.0 V ≤ 3.0 ns 50 pF, 15 pF tPLH, tPHL 12. Transfer characteristics Table 10. Transfer characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); see Figure 8 and Figure 9.
PAGE 9
74VHC14; 74VHCT14 NXP Semiconductors Hex inverting Schmitt trigger mna411 1.5 mna412 5 I CC I CC (mA) (mA) 4 1 3 2 0.5 1 0 0 0 1 2 VI (V) 1 0 3 a. VCC = 3.0 V 2 3 4 V (V) 5 I b. VCC = 4.5 V mna413 6 I CC (mA) 4 2 0 0 2 4 VI (V) 6 c. VCC = 5.5 V Fig 10. Typical 74VHC transfer characteristics 74VHC_VHCT14_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev.
PAGE 10
74VHC14; 74VHCT14 NXP Semiconductors Hex inverting Schmitt trigger mna414 6 mna415 8 I CC I CC (mA) (mA) 6 4 4 2 2 0 0 0 1 2 3 0 4 V (V) 5 I a. VCC = 4.5 V 2 4 VI (V) 6 b. VCC = 5.5 V Fig 11. Typical 74VHCT transfer characteristics 14. Application information R C mna035 1 T 1 0.55 × RC For 74VHC14: f = --- ≈ ------------------------- 1 T 1 0.60 × RC For 74VHCT14: f = --- ≈ ------------------------- Fig 12.
PAGE 11
74VHC14; 74VHCT14 NXP Semiconductors Hex inverting Schmitt trigger 15. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.
PAGE 12
74VHC14; 74VHCT14 NXP Semiconductors Hex inverting Schmitt trigger TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.
PAGE 13
74VHC14; 74VHCT14 NXP Semiconductors Hex inverting Schmitt trigger DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max.
PAGE 14
74VHC14; 74VHCT14 NXP Semiconductors Hex inverting Schmitt trigger 16. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model 17. Revision history Table 12.
PAGE 15
74VHC14; 74VHCT14 NXP Semiconductors Hex inverting Schmitt trigger 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
PAGE 16
NXP Semiconductors 74VHC14; 74VHCT14 Hex inverting Schmitt trigger 20. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 16 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . .