Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal HVQFN 40

1. General description

The ADC1115S125 is a single channel 11-bit Analog-to-Digital Converter (ADC) optimized

for high dynamic performance and low power consumption at sample rates up to

125 Msps. Pipelined architecture and output error correction ensure the ADC1115S125 is

accurate enough to guarantee zero missing codes over the entire operating range.

Supplied from a single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in

CMOS mode, because of a separate digital output supply.

The ADC1115S125 supports the Low Voltage Differential Signalling (LVDS) Double Data

Rate (DDR) output standard. An integrated Serial Peripheral Interface (SPI) allows the

user to easily configure the ADC.

The device also includes a SPI programmable full-scale to allow flexible input voltage

range from 1 V to 2 V (peak-to-peak). With excellent dynamic performance from the

baseband to input frequencies of 170 MHz or more, the ADC1115S125 is ideal for use in

communications, imaging and medical applications - especially in high Intermediate

Frequency (IF) applications because of the integrated input buffer. The input buffer

ensures that the input impedance remains constant and low and the performance

consistent over a wide frequency range.

2. Features and benefits

ADC1115S125

Single 11-bit ADC; 125 Msps with input buffer; CMOS or LVDS

DDR digital outputs

Rev. 2 — 17 December 2010 Product data sheet

 SNR, 66.5 dBFS; SFDR, 86 dBc  Input bandwidth, 600 MHz

 Sample rate up to 125 Msps  Power dissipation, 840 mW including

analog input buffer

 11-bit pipelined ADC core  Serial Peripheral Interface (SPI)

 Clock input divided by 2 for less jitter

contribution

 Duty cycle stabilizer

 Integrated input buffer  Fast OuT-of-Range (OTR) detection

 Flexible input voltage range: 1 V (p-p) to

2 V (p-p)

 Offset binary, two’s complement, gray

code

 CMOS or LVDS DDR digital outputs  Power-down mode and Sleep mode

 Pin compatible with the ADC1415S

series, the ADC1215S series and the

ADC1015S series

 HVQFN40 package

Summary of content (38 pages)

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ADC1115S125 Single 11-bit ADC; 125 Msps with input buffer; CMOS or LVDS DDR digital outputs Rev. 2 — 17 December 2010 Product data sheet 1. General description The ADC1115S125 is a single channel 11-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performance and low power consumption at sample rates up to 125 Msps. Pipelined architecture and output error correction ensure the ADC1115S125 is accurate enough to guarantee zero missing codes over the entire operating range.
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ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs 3. Applications Wireless and wired broadband communications Portable instrumentation Imaging systems Digital predistortion loop, power amplifier linearization Spectral analysis Ultrasound equipment Software defined radio 4. Ordering information Table 1.
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ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs 6. Pinning information 31 DAV 32 n.c. 33 VDDO 34 OGND 35 OTR 36 SCLK/DFS 37 SDIO/ODS 38 CS 39 SENSE 40 VREF terminal 1 index area 31 DAV 32 n.c. 33 VDDO 34 OGND 35 OTR 36 SCLK/DFS 37 SDIO/ODS 38 CS terminal 1 index area 39 SENSE 40 VREF 6.1 Pinning REFB 1 30 n.c. REFB 1 30 n.c. REFT 2 29 n.c. REFT 2 29 n.c. AGND 3 28 LOW_D0_P AGND 3 28 n.c.
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ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs Table 2.
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ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs Table 3. Pin description …continued (LVDS/DDR) digital outputs) Symbol Pin [1] Type [2] Description n.c. 30 - not connected DAVM 31 O data valid output clock, complement DAVP 32 O data valid output clock, true [1] Pins 1 to 16 and pins 33 to 40 are the same for both CMOS and LVDS DDR outputs (see Table 2) [2] P: power supply; G: ground; I: input; O: output; I/O: input/output. 7.
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ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs Table 6.
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ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs Table 6. Static characteristics[1] …continued Symbol Parameter Conditions Min Typ Max Unit VO(dif) differential output voltage output buffer current set to 3.5 mA - 350 - mV CO output capacitance - 3 - pF Analog inputs: pins INP and INM II input current −5 - +5 μA RI input resistance - 550 - Ω CI input capacitance - 1.3 - pF VI(cm) common-mode input voltage 0.9 1.
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ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs 10. Dynamic characteristics 10.1 Dynamic characteristics Table 7.
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ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs 10.2 Clock and digital output timing Table 8. Clock and digital output timing characteristics[1] Symbol Parameter Conditions Min Typ Max Unit Clock timing input: pins CLKP and CLKM fclk clock frequency tlat(data) data latency time δclk clock duty cycle 100 - 125 MHz - 13.5 - clock cycles DCS_EN = 1 30 50 70 % DCS_EN = 0 45 50 55 % td(s) sampling delay time - 0.
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ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs N+1 N td(s) N+2 tclk CLKP CLKM tPD (N − 14) (N − 13) (N − 12) (N − 11) DATA tsu tPD th DAV tclk 005aaa060 Fig 4. CMOS mode timing N+1 N td(s) N+2 tclk CLKP CLKM tPD (N − 14) (N − 13) (N − 12) (N − 11) Dx_Dx + 1_P Dx Dx + 1 Dx Dx + 1 Dx Dx + 1 Dx Dx + 1 Dx Dx + 1 Dx_Dx + 1_M tsu th tsu th tPD DAVP DAVM tclk Fig 5.
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ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs 10.3 SPI timings Table 9.
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ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs 10.
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ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs 001aam659 90 001aam660 75 SFDR (dBc) SNR (dBFS) 86 73 82 71 78 69 74 67 70 65 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 0.5 1.0 1.5 2.0 2.5 VI(cm) (V) Fig 11. Spurious-free dynamic range as a function of common-mode input voltage (Vi(cm)) 3.0 3.5 VI(cm) (V) Fig 12. Signal-to-noise ratio as a function of common-mode input voltage (Vi(cm)) 11. Application information 11.
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ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs 11.1.2 Operating mode selection The active ADC1115S125 operating mode (Power-up, Power-down or Sleep) can be selected via the SPI interface (see Table 19) or using pins PWD and OE in Pin control mode, as described in Table 10. Table 10.
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ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs package ESD parasitics switch INP Ron = 15 Ω 8 internal clock 4 pF sampling capacitor INPUT BUFFER switch INM Ron = 15 Ω 7 internal clock 4 pF sampling capacitor 005aaa107 Fig 14.
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ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs 11.2.2 Transformer The configuration of the transformer circuit is determined by the input frequency. The configuration shown in Figure 15 would be suitable for a baseband application. ADT1-1WT Analog input 100 nF 100 nF INP 50 Ω 100 nF 100 nF INM VCM 100 nF 100 nF 005aaa108 Fig 15.
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ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs 11.3 System reference and power management 11.3.1 Internal/external references The ADC1115S125 has a stable and accurate built-in internal reference voltage to adjust the ADC full-scale. This reference voltage can be set internally via SPI or with pins VREF and SENSE (programmable in 1 dB steps between 0 dB and −6 dB via control bits INTREF[2:0] when bit INTREF_EN = logic 1; see Table 21).
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ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs Figure 18 to Figure 21 illustrate how to connect the SENSE and VREF pins to select the required reference voltage source. VREF VREF 330 pF 330 pF REFERENCE EQUIVALENT SCHEMATIC REFERENCE EQUIVALENT SCHEMATIC SENSE SENSE 005aaa117 005aaa116 Fig 18. Internal reference, 2 V (p-p) full scale Fig 19. Internal reference, 1 V (p-p) full scale VREF V 0.
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ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs 11.4 Clock input 11.4.1 Drive modes The ADC1115S can be driven differentially (LVPECL). It can also be driven by a single-ended Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) signal connected to pin CLKP (pin CLKM should be connected to ground via a capacitor) or CLKM (pin CLKP should be connected to ground via a capacitor).
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ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs 11.4.2 Equivalent input circuit The equivalent circuit of the input clock buffer is shown in Figure 24. The common-mode voltage of the differential input stage is set via internal 5 kΩ resistors. Package ESD Parasitics CLKP Vcm(clk) SE_SEL SE_SEL 5 kΩ 5 kΩ CLKM 005aaa056 Vcm(clk) = common-mode voltage of the differential input stage. Fig 24.
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ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs 11.5 Digital outputs 11.5.1 Digital output buffers: CMOS mode The digital output buffers can be configured as CMOS by setting bit LVDS_CMOS to logic 0 (see Table 23). Each digital output has a dedicated output buffer. The equivalent circuit of the CMOS digital output buffer is shown in Figure 25. The buffer is powered by a separate OGND/VDDO to ensure 1.8 V to 3.
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ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs 11.5.2 Digital output buffers: LVDS DDR mode The digital output buffers can be configured as LVDS DDR by setting bit LVDS_CMOS to logic 1 (see Table 23). VCCO 3.5 mA typ − + DnP/Dn + 1P 100 Ω RECEIVER DnM/Dn + 1M − + OGND 005aaa058 Fig 26.
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ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs Table 13. LVDS DDR output register 2 …continued LVDS_INT_TER[2:0] Resistor value (Ω) 101 100 110 81 111 60 11.5.3 DAta Valid (DAV) output clock A data valid output clock signal (DAV) is provided that can be used to capture the data delivered by the ADC1115S125. Detailed timing diagrams for CMOS and LVDS DDR modes are provided in Figure 4 and Figure 5 respectively. 11.5.
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ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs 11.5.7 Output codes versus input voltage Table 15. Output codes VINP − VINM Offset binary Two’s complement OTR pin < −1 000 0000 0000 100 0000 0000 1 −1.0000000 000 0000 0000 100 0000 0000 0 −0.9990234 000 0000 0001 100 0000 0001 0 −0.9980469 000 0000 0010 100 0000 0010 0 −0.9970703 000 0000 0011 100 0000 0011 0 −0.996093 000 0000 0100 100 0000 0100 0 .... .... .... 0 −0.
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ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs Table 17. Number of data bytes to be transferred after the instruction bytes W1 W0 Number of bytes transmitted 0 0 1 byte 0 1 2 bytes 1 0 3 bytes 1 1 4 bytes or more Bits A12 to A0 indicate the address of the register being accessed. In the case of a multiple byte transfer, this address is the first register to be accessed. An address counter is increased to access subsequent addresses.
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ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs CS SCLK (Data format) SDIO (CMOS LVDS DDR) Offset binary, LVDS DDR default mode at start-up 005aaa063 Fig 29. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR CS SCLK (Data format) SDIO (CMOS LVDS DDR) two's complement, CMOS default mode at start-up 005aaa064 Fig 30.
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ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs Table 19. Reset and operating mode control register (address 0005h) bit description Default values are highlighted.
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ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs Table 21. Internal reference control register (address 0008h) bit description Default values are highlighted. Bit Symbol 7 to 4 - 3 INTREF_EN 2 to 0 INTREF[2:0] Access Value Description 0000 not used R/W programmable internal reference enable 0 disable 1 active R/W programmable internal reference 000 0 dB (FS = 2 V) 001 −1 dB (FS = 1.78 V) 010 −2 dB (FS = 1.
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ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs Table 23. Output data standard control register (address 0011h) bit description …continued Default values are highlighted. Bit Symbol Access 1 to 0 DATA_FORMAT[1:0] R/W Value Description output data format 00 offset binary 01 two’s complement 10 gray code 11 offset binary Table 24. Output clock register (address 0012h) bit description Default values are highlighted.
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ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs Table 26. Test pattern register 1 (address 0014h) bit description …continued Default values are highlighted. Bit Symbol Access 2 to 0 TESTPAT_SEL[2:0] R/W Value Description digital test pattern select 000 off 001 mid scale 010 −FS 011 +FS 100 toggle ‘1111..1111’/’0000..0000’ 101 custom test pattern 110 ‘1010..1010.’ 111 ‘010..1010’ Table 27.
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ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs Table 30. CMOS output register (address 0020h) bit description Default values are highlighted. Bit Symbol 7 to 4 - 3 to 2 DAV_DRV[1:0] 1 to 0 DATA_DRV[1:0] Access Value Description 0000 not used R/W drive strength for DAV CMOS output buffer 00 low 01 medium 10 high 11 very high R/W drive strength for DATA CMOS output buffer 00 low 01 medium 10 high 11 very high Table 31.
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ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs Table 32. LVDS DDR output register 2 (address 0022h) bit description Default values are highlighted.
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ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs 12. Package outline HVQFN40: plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 x 6 x 0.85 mm A B D SOT618-6 terminal 1 index area E A A1 c detail X e1 1/2 e e 11 20 C C A B C v w b y1 C y L 21 10 e e2 Eh 1/2 e 1 terminal 1 index area 30 40 31 X Dh 0 2.5 scale Dimensions Unit A(1) A1 b max 1.00 0.05 0.30 nom 0.85 0.02 0.21 min 0.80 0.00 0.
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ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs 13. Revision history Table 33. Revision history Document ID Release date Data sheet status Change Supersedes notice ADC1115S125 v.2 20101217 Product data sheet - Modifications: ADC1115S125 v.1 ADC1115S125 Product data sheet • • • ADC1115S125 v.1 Data sheet status changed from Preliminary to Product. Text and drawings updated throughout entire data sheet. Section 10.
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ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs 14. Legal information 14.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
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ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements.
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ADC1115S125 NXP Semiconductors 11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs 16. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 10.1 10.2 10.3 10.4 11 11.1 11.1.1 11.1.2 11.1.3 11.1.4 11.2 11.2.1 11.2.2 11.3 11.3.1 11.3.2 11.3.3 11.3.4 11.4 11.4.1 11.4.2 11.4.3 11.4.4 11.5 11.5.1 11.5.2 11.5.3 11.5.4 11.5.5 11.5.6 11.5.7 11.6 11.6.1 11.6.2 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . .