Datasheet

ADC1115S125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 17 December 2010 10 of 38
NXP Semiconductors
ADC1115S125
11-bit, 125 Msps ADC; input buffer; CMOS or LVDS DDR digital outputs
Fig 4. CMOS mode timing
Fig 5. LDVS DDR mode timing
(N − 12)
t
d(s)
t
clk
N
N + 1
N + 2
t
clk
t
su
t
PD
t
h
t
PD
CLKP
CLKM
DATA
DAV
005aaa06
0
(N − 11)(N − 13)(N − 14)
005aaa061
(N − 14)
t
d(s)
t
clk
N
N + 1
N + 2
CLKP
CLKM
DAVP
DAVM
t
su
t
h
t
h
t
su
t
PD
t
PD
D
x
_D
x + 1
_P
D
x
_D
x + 1
_M
D
x
D
x + 1
D
x + 1
D
x + 1
D
x + 1
D
x + 1
D
x
D
x
D
x
D
x
(N − 11)(N − 12)(N − 13)
t
clk