Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal HVQFN 64

1. General description

The ADC1212D is a dual channel 12-bit Analog-to-Digital Converter (ADC) optimized for

high dynamic performances and low power consumption at sample rates up to 125 Msps.

Pipelined architecture and output error correction ensure the ADC1212D is accurate

enough to guarantee zero missing codes over the entire operating range. Supplied from a

single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in

Complementary Metal Oxide Semiconductor (CMOS) mode, because of a separate digital

output supply. It supports the Low Voltage Differential Signalling (LVDS) Double Data Rate

(DDR) output standard. An integrated Serial Peripheral Interface (SPI) allows the user to

easily configure the ADC. The device also includes a programmable full-scale SPI to allow

a flexible input voltage range of 1 V (p-p) to 2 V (p-p). With excellent dynamic

performance from the baseband to input frequencies of 170 MHz or more, the ADC1212D

is ideal for use in communications, imaging and medical applications.

2. Features and benefits

3. Applications

ADC1212D series

Dual 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps;

CMOS or LVDS DDR digital outputs

Rev. 2 — 4 March 2011 Product data sheet

 SNR, 70 dBFS  Input bandwidth, 600 MHz

 SFDR, 86 dBc  Power dissipation, 855 mW at 80 Msps

 Sample rate up to 125 Msps  Serial Peripheral Interface (SPI)

 Clock input divided by 2 to reduce jitter

contribution

 Duty cycle stabilizer

 Single 3 V supply  Fast OuT-of-Range (OTR) detection

 Flexible input voltage range:

1Vto2V(p-p)

 Offset binary, two’s complement, gray

code

 CMOS or LVDS DDR digital outputs  Power-down and Sleep modes

 Pin and software compatible with

ADC1412D series and ADC1112D125.

 HVQFN64 package

 Wireless and wired broadband

communications

 Spectral analysis

 Portable instrumentation  Ultrasound equipment

 Imaging systems  Software defined radio

Summary of content (42 pages)

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ADC1212D series Dual 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs Rev. 2 — 4 March 2011 Product data sheet 1. General description The ADC1212D is a dual channel 12-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performances and low power consumption at sample rates up to 125 Msps. Pipelined architecture and output error correction ensure the ADC1212D is accurate enough to guarantee zero missing codes over the entire operating range.
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ADC1212D series NXP Semiconductors Dual 12-bit ADC: CMOS or LVDS DDR digital outputs 4. Ordering information Table 1. Ordering information Type number fs (Msps) Package Name Description Version ADC1212D125HN/C1 125 HVQFN64 plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 9  9  0.85 mm SOT804-3 ADC1212D105HN/C1 105 HVQFN64 plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 9  9  0.
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ADC1212D series NXP Semiconductors Dual 12-bit ADC: CMOS or LVDS DDR digital outputs 6. Pinning information 6.1 CMOS outputs selected 49 VDDO 50 VDDO 51 DA4 52 DA5 53 DA6 54 DA7 55 DA8 56 DA9 57 DA10 58 DA11 59 OTRA 60 DECA 61 VDDA INAP 1 48 DA3 INAM 2 47 DA2 AGND 3 46 DA1 VCMA 4 45 DA0 REFAT 5 44 n.c. REFAB 6 43 n.c. AGND 7 42 DAV CLKP 8 CLKM 9 41 n.c. ADC1212D HVQFN64 40 n.c.
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ADC1212D series NXP Semiconductors Dual 12-bit ADC: CMOS or LVDS DDR digital outputs Table 2.
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ADC1212D series NXP Semiconductors Dual 12-bit ADC: CMOS or LVDS DDR digital outputs Table 2.
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ADC1212D series NXP Semiconductors Dual 12-bit ADC: CMOS or LVDS DDR digital outputs 6.2.2 Pin description Table 3.
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ADC1212D series NXP Semiconductors Dual 12-bit ADC: CMOS or LVDS DDR digital outputs 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit pins DA11 to DA0 and DB11 to DB0 or pins DA10_DA11_P to DA0_DA1_P, DA10_DA11_M to DA0_DA1_M, DB10_DB11_P to DB0_DB1_P and DB10_DB11_M to DB0_DB1_M 0.4 +3.9 V +3.9 V VO output voltage VDDA analog supply voltage 0.4 VDDO output supply voltage 0.4 +3.
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ADC1212D series NXP Semiconductors Dual 12-bit ADC: CMOS or LVDS DDR digital outputs Table 6.
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ADC1212D series NXP Semiconductors Dual 12-bit ADC: CMOS or LVDS DDR digital outputs Table 6. Symbol Static characteristics[1] …continued Parameter Conditions Min Typ Max Unit Digital outputs, LVDS DDR mode: pins DA10_DA11_P to DA0_DA1_P, DA10_DA11_M to DA0_DA1_M, DB10_DB11_P to DB0_DB1_P, DB10_DB11_M to DB0_DB1_M; DAVP and DAVM Output levels, VDDO = 3 V only, RL = 100  VO(offset) output offset voltage output buffer current set to 3.5 mA - 1.
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors ADC1212D_SER Product data sheet 10. Dynamic characteristics 10.
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ADC1212D series NXP Semiconductors Dual 12-bit ADC: CMOS or LVDS DDR digital outputs N N+1 td(s) N+2 tclk CLKP CLKM tPD (N − 14) (N − 13) (N − 12) (N − 11) DATA tsu tPD th DAV tclk 005aaa060 tclk = 1 / fclk Fig 4.
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ADC1212D series NXP Semiconductors Dual 12-bit ADC: CMOS or LVDS DDR digital outputs 10.3 SPI timings Table 9.
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ADC1212D series NXP Semiconductors Dual 12-bit ADC: CMOS or LVDS DDR digital outputs 10.4 Typical characteristics 001aam619 3.2 001aam614 16 C (pF) R (kΩ) 3.0 12 2.8 8 2.6 4 2.4 0 50 Fig 7. 150 250 350 450 550 f (MHz) Capacitance as a function of frequency 001aam616 100 SFDR (dBc) 50 Fig 8.
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ADC1212D series NXP Semiconductors Dual 12-bit ADC: CMOS or LVDS DDR digital outputs 001aam617 92 SFDR (dBc) 88 001aam618 80 (1) SNR (dBFS) (2) 60 (1) (2) (3) (3) 84 40 80 20 10 30 50 70 δ (%) 90 10 30 50 70 δ (%) (1) Tamb = 40 C/typical supply voltages (1) Tamb = 40 C/typical supply voltages (2) Tamb = +25 C/typical supply voltages (2) Tamb = +25 C/typical supply voltages (3) Tamb = +90 C/typical supply voltages (3) Tamb = +90 C/typical supply voltages Fig 11.
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ADC1212D series NXP Semiconductors Dual 12-bit ADC: CMOS or LVDS DDR digital outputs 11. Application information 11.1 Device control The ADC1212D can be controlled via the Serial Peripheral Interface (SPI control mode) or directly via the I/O pins (Pin control mode). 11.1.1 SPI and Pin control modes The device enters Pin control mode at power-up and remains in this mode as long as pin CS is held HIGH. In Pin control mode, the SPI pins SDIO, CS and SCLK are used as static control pins.
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ADC1212D series NXP Semiconductors Dual 12-bit ADC: CMOS or LVDS DDR digital outputs 11.1.4 Selecting the output data format The output data format can be selected via the SPI interface (offset binary, two’s complement or gray code; see Table 24) or by using pin DFS in Pin control mode (offset binary or two’s complement). Offset binary is selected when DFS is LOW. When DFS is HIGH, two’s complement is selected. 11.2 Analog inputs 11.2.
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ADC1212D series NXP Semiconductors Dual 12-bit ADC: CMOS or LVDS DDR digital outputs INAP/ INBP R C INAM/ INBM R 001aan679 Fig 17. Anti-kickback circuit The component values are determined by the input frequency and should be selected so as not to affect the input bandwidth. Table 11. RC coupling versus input frequency, typical values Input frequency (MHz) R () C (pF) 3 25 12 70 12 8 170 12 8 11.2.
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ADC1212D series NXP Semiconductors Dual 12-bit ADC: CMOS or LVDS DDR digital outputs ADT1-1WT Analog input 100 nF ADT1-1WT 50 Ω 12 Ω INAP/INBP 50 Ω 8.2 pF 50 Ω 100 nF 50 Ω 12 Ω INAM/INBM VCMA/VCMB 100 nF 100 nF 005aaa095 Fig 19. Dual transformer configuration suitable for high intermediate frequency application 11.3 System reference and power management 11.3.
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ADC1212D series NXP Semiconductors Dual 12-bit ADC: CMOS or LVDS DDR digital outputs REFAT/ REFBT REFAB/ REFBB REFERENCE AMP VREF EXT_ref BUFFER EXT_ref BANDGAP REFERENCE ADC CORE SENSE SELECTION LOGIC 001aan670 Fig 20. Reference equivalent schematic If bit INTREF_EN is set to logic 0, the reference voltage is determined either internally or externally as detailed in Table 12. Table 12.
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ADC1212D series NXP Semiconductors Dual 12-bit ADC: CMOS or LVDS DDR digital outputs VREF VREF 330 pF 330 pF REFERENCE EQUIVALENT SCHEMATIC REFERENCE EQUIVALENT SCHEMATIC SENSE SENSE 005aaa117 005aaa116 Fig 21. Internal reference, 2 V (p-p) full-scale Fig 22. Internal reference, 1 V (p-p) full-scale VREF VREF V 0.1 μF 330 pF REFERENCE EQUIVALENT SCHEMATIC REFERENCE EQUIVALENT SCHEMATIC SENSE SENSE VDDA 005aaa118 005aaa119 Fig 23.
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ADC1212D series NXP Semiconductors Dual 12-bit ADC: CMOS or LVDS DDR digital outputs Package ESD Parasitics COMMON MODE REFERENCE VCMA/VCMB 1.5 V 0.1 μF ADC CORE 005aaa099 Fig 25. Equivalent schematic of the common-mode reference circuit 11.3.4 Biasing The common-mode input voltage (VI(cm)) on pins INAP/INBP and INAM/INBM should be set externally to 0.5VDDA for optimal performance and should always be between 0.9 V and 2 V (see Table 6). 11.4 Clock input 11.4.
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ADC1212D series NXP Semiconductors Dual 12-bit ADC: CMOS or LVDS DDR digital outputs Sine clock input CLKP Sine clock input CLKP CLKM CLKM 005aaa173 005aaa054 a. Sine clock input b. Sine clock input (with transformer) CLKP LVPECL clock input CLKM 005aaa172 c. LVPECL clock input Fig 27. Differential clock input 11.4.2 Equivalent input circuit The equivalent circuit of the input clock buffer is shown in Figure 28.
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ADC1212D series NXP Semiconductors Dual 12-bit ADC: CMOS or LVDS DDR digital outputs Single-ended or differential clock inputs can be selected via the SPI interface (see Table 22). If single-ended is enabled, the input pin (CLKM or CLKP) is selected via control bit SE_SEL. If single-ended is implemented without setting bit SE_SEL to the appropriate value, the unused pin should be connected to ground via a capacitor. 11.4.
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ADC1212D series NXP Semiconductors Dual 12-bit ADC: CMOS or LVDS DDR digital outputs The output resistance is 50  and is the combination of an internal resistor and the equivalent output resistance of the buffer. There is no need for an external damping resistor. The drive strength of both DATA and DAV buffers can be programmed via the SPI in order to adjust the rise and fall times of the output digital signals (see Table 31). 11.5.
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ADC1212D series NXP Semiconductors Dual 12-bit ADC: CMOS or LVDS DDR digital outputs Table 14. LVDS DDR output register 2 LVDS_INT_TER[2:0] Resistor value () 000 no internal termination 001 300 010 180 011 110 100 150 101 100 110 81 111 6 11.5.3 DAta Valid (DAV) output clock A data valid output clock signal (DAV) is provided that can be used to capture the data delivered by the ADC1212D.
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ADC1212D series NXP Semiconductors Dual 12-bit ADC: CMOS or LVDS DDR digital outputs 11.5.6 Test patterns For test purposes, the ADC1212D can be configured to transmit one of a number of predefined test patterns (via bits TESTPAT_SEL[2:0]; see Table 27). A custom test pattern can be defined by the user (TESTPAT_USER[11:4]; see Table 28 and TESTPAT_USER[3:0]; see Table 29) and is selected when TESTPAT_SEL[2:0] = 101. The selected test pattern is transmitted regardless of the analog input. 11.5.
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ADC1212D series NXP Semiconductors Dual 12-bit ADC: CMOS or LVDS DDR digital outputs Table 17. Instruction bytes for the SPI MSB LSB Bit 7 6 5 4 3 2 Description R/W[1] W1[2] W0[2] 1 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 [1] Bit R/W indicates whether it is a read (logic 1) or a write (logic 0) operation. [2] Bits W1 and W0 indicate the number of bytes to be transferred (see Table 18). Table 18.
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ADC1212D series NXP Semiconductors Dual 12-bit ADC: CMOS or LVDS DDR digital outputs When the ADC1212D enters SPI control mode, the output data format (two’s complement or offset binary) is determined by the level on pin SCLK (gray code can only be selected via the SPI). Once in SPI control mode, the output data format can be changed via bit DATA_FORMAT[1:0] (see Table 24). CS SCLK (Data format) SDIO (CMOS LVDS DDR) Offset binary, LVDS DDR default mode at start-up 005aaa063 Fig 33.
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ADC1212D series NXP Semiconductors Dual 12-bit ADC: CMOS or LVDS DDR digital outputs Table 20. Channel index control register (address 0003h) bit description Default values are highlighted. Bit Symbol 7 to 2 1 0 Access Value RESERVED[5:0] - 111111 ADCB R/W ADCA Description reserved next SPI command for ADC B 0 ADC B not selected 1 ADC B selected R/W next SPI command for ADC A 0 ADC A not selected 1 ADC A selected Table 21.
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ADC1212D series NXP Semiconductors Dual 12-bit ADC: CMOS or LVDS DDR digital outputs Table 23. Internal reference control register (address 0008h) bit description Default values are highlighted. Bit Symbol Access Value Description 7 to 4 - - 0000 not used 3 INTREF_EN R/W 2 to 0 INTREF[2:0] programmable internal reference enable 0 disable 1 active R/W programmable internal reference 000 0 dB (FS = 2 V) 001 1 dB (FS = 1.78 V) 010 2 dB (FS = 1.59 V) 011 3 dB (FS = 1.
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ADC1212D series NXP Semiconductors Dual 12-bit ADC: CMOS or LVDS DDR digital outputs Table 25. Output clock register (address 0012h) bit description Default values are highlighted.
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ADC1212D series NXP Semiconductors Dual 12-bit ADC: CMOS or LVDS DDR digital outputs Table 28. Test pattern register 2 (address 0015h) bit description Default values are highlighted. Bit Symbol Access Value Description 7 to 0 TESTPAT_USER[11:4] R/W 0000 0000 custom digital test pattern (bits 11 to 4) Table 29. Test pattern register 3 (address 0016h) bit description Default values are highlighted.
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ADC1212D series NXP Semiconductors Dual 12-bit ADC: CMOS or LVDS DDR digital outputs Table 32. LVDS DDR output register 1 (address 0021h) bit description Default values are highlighted. Bit Symbol Access Value Description 7 to 6 - - 00 not used 5 RESERVED - 0 reserved 4 to 3 DAVI[1:0] R/W 2 RESERVED - 1 to 0 DATAI[1:0] R/W LVDS current for DAV LVDS buffer 00 3.5 mA 01 4.5 mA 10 1.25 mA 11 2.5 mA 0 reserved LVDS current for DATA LVDS buffer 00 3.5 mA 01 4.5 mA 10 1.
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ADC1212D series NXP Semiconductors Dual 12-bit ADC: CMOS or LVDS DDR digital outputs 12. Package outline HVQFN64: plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 9 x 9 x 0.85 mm A B D SOT804-3 terminal 1 index area E A1 A c detail X e1 1/2 e e L 17 32 C C A B C v w b y1 C y 33 16 e e2 Eh 1/2 e 1 terminal 1 index area 48 64 49 X Dh 0 2.5 scale Dimensions Unit A A1 b max 1.00 0.05 0.30 nom 0.85 0.02 0.21 min 0.80 0.00 0.
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ADC1212D series NXP Semiconductors Dual 12-bit ADC: CMOS or LVDS DDR digital outputs 13. Abbreviations Table 34.
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ADC1212D series NXP Semiconductors Dual 12-bit ADC: CMOS or LVDS DDR digital outputs 14. Revision history Table 35. Revision history Document ID Release date Data sheet status Change notice Supersedes ADC1212D_SER v.2 20110304 Product data sheet - ADC1212D_SER v.1 Modifications: ADC1212D_SER v.1 ADC1212D_SER Product data sheet • • • • Data sheet status changed from Preliminary to Product. Text and drawings updated throughout entire data sheet. Section 10.
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ADC1212D series NXP Semiconductors Dual 12-bit ADC: CMOS or LVDS DDR digital outputs 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
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ADC1212D series NXP Semiconductors Dual 12-bit ADC: CMOS or LVDS DDR digital outputs Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements.
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ADC1212D series NXP Semiconductors Dual 12-bit ADC: CMOS or LVDS DDR digital outputs 17. Contents 1 2 3 4 5 6 6.1 6.1.1 6.1.2 6.2 6.2.1 6.2.2 7 8 9 10 10.1 10.2 10.3 10.4 11 11.1 11.1.1 11.1.2 11.1.3 11.1.4 11.2 11.2.1 11.2.2 11.2.3 11.3 11.3.1 11.3.2 11.3.3 11.3.4 11.4 11.4.1 11.4.2 11.4.3 11.4.4 11.5 11.5.1 11.5.2 11.5.3 11.5.4 11.5.5 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . .