Information

NXP Semiconductors
AN11022
CLRC663 Quickstart Guide
To connect a different antenna, J1-J7 can be used (after cutting the board).
Table 8. Antenna section connector
Connector via
Signal
J1
Tx2
J2
Tx1
J3
GND
J4
RxP
J5
RxN
J6
GND
J7
GND
4. Register Settings for different modes and features
4.1 EMD suppression
The EMD suppression feature is only for ISO 14443 use cases.
If an error occurs within the first three bytes or the frame is < 3 bytes, this frame is
seen as EMD and ignored. If RxForceCRCWrite is set, the FIFO should not be read out
before three bytes are written into. The FIFO is cleared automatically in case of an EMD
error. A collision is treated as error.
To activate the EMD suppression the EMD_SUP Bit in the RxCtrl Register has to be set.
(Table 9
)
Table 9. RxCtrl_Reg register (address 35h); reset value: 04h
Bit
7
6
5
4
3
0 - 2
Symbol
RxAllow
Bits
Rx
Multiple
RxEOF
Type
EGT_
Check
EMD_
Sup
Baud rate
Access rights
r/w
r/w
r/w
r/w
r/w
r/w
AN11022 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2015. All rights reserved.
Application note
COMPANY PUBLIC
Rev. 1.2 — 14 January 2015
205912
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