CLRC632 Standard multi-protocol reader solution Rev. 3.7 — 27 February 2014 073937 Product data sheet COMPANY PUBLIC 1. Introduction This data sheet describes the functionality of the CLRC632 Integrated Circuit (IC). It includes the functional and electrical specifications and from a system and hardware viewpoint gives detailed information on how to design-in the device. Remark: The CLRC632 supports all variants of the MIFARE Mini, MIFARE 1K, MIFARE 4K and MIFARE Ultralight RF identification protocols.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution The internal transmitter module (Section 9.9 on page 31) can directly drive an antenna designed for a proximity operating distance up to 100 mm without any additional active circuitry. A parallel interface can be directly connected to any 8-bit microprocessor to ensure reader/terminal design flexibility. In addition, Serial Peripheral Interface (SPI) compatibility is supported (see Section 9.1.4 on page 9). 3. Features and benefits 3.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution Subscriber services Banking systems Digital content systems 5. Quick reference data Table 1. Quick reference data Symbol Parameter Tamb Conditions Min Typ Max Unit ambient temperature 40 - +150 C Tstg storage temperature 40 - +150 C VDDD digital supply voltage 0.5 5 6 V VDDA analog supply voltage 0.5 5 6 V VDD(TVDD) TVDD supply voltage 0.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 7.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 8. Pinning information OSCIN 1 32 OSCOUT IRQ 2 31 RSTPD MFIN 3 30 VMID MFOUT 4 29 RX TX1 5 28 AVSS TVDD 6 27 AUX TX2 7 26 AVDD TVSS 8 NCS 9 CLRC632 25 DVDD 24 A2/SCK 23 A1 NWR/R/NW/nWrite 10 22 A0/nWait/MOSI NRD/NDS/nDStrb 11 21 ALE/AS/nAStrb/NSS DVSS 12 AD0/D0 13 20 D7/AD7 AD1/D1 14 19 D6/AD6 AD2/D2 15 18 D5/AD5 17 D4/AD4 AD3/D3 16 001aaj630 Fig 2. CLRC632 pin configuration 8.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution Table 3.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 9. Functional description 9.1 Digital interface 9.1.1 Overview of supported microprocessor interfaces The CLRC632 supports direct interfacing to various 8-bit microprocessors. Alternatively, the CLRC632 can be connected to a PC’s Enhanced Parallel Port (EPP). Table 4 shows the parallel interface signals supported by the CLRC632. Table 4.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 9.1.3 Connection to different microprocessor types The connection to various microprocessor types is shown in Table 5. Table 5. CLRC632 pins 9.1.3.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 9.1.3.2 Common read and write strobe address bus (A3 to An) ADDRESS DECODER DEVICE NCS non-multiplexed address ADDRESS DECODER LOW A2 HIGH address bus (A0 to A2) A1 LOW A0 to A2 data bus (D0 to D7) A0 multiplexed address/data (AD0 to AD7) AD0 to AD7 D0 to D7 HIGH Address strobe (AS) ALE Data strobe (NDS) Read/Write (R/NW) DEVICE NCS ALE Data strobe (NDS) NRD NRD Read/Write (R/NW) NWR NWR 001aak608 Fig 4.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution Table 6. SPI compatibility CLRC632 pins SPI pins ALE NSS A2 SCK A1 LOW A0 MOSI NRD HIGH NWR HIGH NCS LOW D7 to D1 do not connect D0 MISO Figure 6 shows the microprocessor connection to the CLRC632 using SPI. DEVICE NCS LOW SCK A2 LOW A1 MOSI A0 MISO D0 NSS ALE 001aak610 Fig 6.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution Table 8. SPI read address Address (MOSI) Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) byte 0 1 address address address address address address reserved byte 1 to byte n reserved address address address address address address reserved byte n + 1 [1] 9.1.4.2 0 0 0 0 0 0 0 0 All reserved bits must be set to logic 0. SPI write data The structure shown in Table 9 must be used to write data using SPI.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 9.2 Memory organization of the EEPROM Table 11. EEPROM memory organization diagram Block CLRC632 Product data sheet COMPANY PUBLIC Position Address Byte address Access Memory content Refer to 0 0 00h to 0Fh R product information field Section 9.2.1 on page 13 1 1 10h to 1Fh R/W Section 9.2.2.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 9.2.1 Product information field (read only) Table 12.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution Remark: The following points apply to initialization: • the Page register (addressed using 10h, 18h, 20h, 28h) is skipped and not initialized. • make sure that all PreSetxx registers are not changed. • make sure that all register bits that are reserved are set to logic 0. 9.2.2.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution Table 15.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 9.2.2.3 Register initialization file (read/write) The EEPROM memory content from block address 3 to 7 can initialize register sub addresses 10h to 2Fh when the LoadConfig command is executed (see Section 11.5.1 on page 95). This command requires the EEPROM starting byte address as a two byte argument for the initialization procedure. The byte assignment is shown in Table 16. Table 16.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution Table 17.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 9.2.3 Crypto1 keys (write only) MIFARE security requires specific cryptographic keys to encrypt data stream communication on the contactless interface. These keys are called Crypto1 keys. 9.2.3.1 Key format Keys stored in the EEPROM are written in a specific format. Each key byte must be split into lower four bits k0 to k3 (lower nibble) and the higher four bits k4 to k7 (higher nibble).
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 9.3 FIFO buffer An 8 64 bit FIFO buffer is used in the CLRC632 to act as a parallel-to-parallel converter. It buffers both the input and output data streams between the microprocessor and the internal circuitry of the CLRC632. This makes it possible to manage data streams up to 64 bytes long without needing to take timing constraints into account. 9.3.1 Accessing the FIFO buffer 9.3.1.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 9.3.3 FIFO buffer status information The microprocessor can get the following FIFO buffer status data: • • • • the number of bytes stored in the FIFO buffer: bits FIFOLength[6:0] the FIFO buffer full warning: bit HiAlert the FIFO buffer empty warning: bit LoAlert the FIFO buffer overflow warning: bit FIFOOvfl. Remark: Setting the FlushFIFO bit clears the FIFOOvfl bit.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 9.4.1 Interrupt sources overview Table 20 shows the integrated interrupt flags, related source and setting condition. The interrupt TimerIRq flag bit indicates an interrupt set by the timer unit. Bit TimerIRq is set when the timer decrements from one down to zero (bit TAutoRestart disabled) or from one to the TReLoadValue[7:0] with bit TAutoRestart enabled.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution If any interrupt request flag is set to logic 1 (showing that an interrupt request is pending) and the corresponding interrupt enable flag is set, the PrimaryStatus register IRq flag bit is set to logic 1. Different interrupt sources can activate simultaneously because all interrupt request bits are OR’ed, coupled to the IRq flag and then forwarded to pin IRQ. 9.4.2.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 9.4.4 Register overview interrupt request system Table 22 shows the related interrupt request system flags in alphabetic order. Table 22.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 9.5.1 Timer unit implementation 9.5.1.1 Timer unit block diagram Figure 8 shows the block diagram of the timer module. TStartTxBegin TReloadValue[7:0] TxBegin Event TStartTxEnd PARALLEL IN TxEnd Event START COUNTER/ PARALLEL LOAD TAutoRestart TStartNow Q S COUNTER MODULE (x ≤ x − 1) TRunning Q R TStopNow STOP COUNTER RxEnd Event TStopRxEnd RxBegin Event TStopRxBegin TPreScaler[4:0] 13.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution The timer is started immediately by loading a value from the TimerReload register into the counter module.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 9.5.1.5 TimeSlotPeriod When sending I-CODE1 Quit frames, it is necessary to generate the exact chronological relationship to the start of the command frame. If at the end of command execution TimeSlotPeriod > 0, the TimeSlotPeriod starts. If the FIFO buffer contains data when the end of TimeSlotPeriod is reached, the data is sent. If the FIFO buffer is empty nothing happens.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 9.5.2 Using the timer unit functions 9.5.2.1 Time-out and WatchDog counters After starting the timer using TReloadValue[7:0], the timer unit decrements the TimerValue register beginning with a given start event. If a given stop event occurs, such as a bit being received from the card, the timer unit stops without generating an interrupt.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 9.6 Power reduction modes 9.6.1 Hard power-down Hard power-down is enabled when pin RSTPD is HIGH. This turns off all internal current sinks including the oscillator. All digital input buffers are separated from the input pads and defined internally (except pin RSTPD itself). The output pins are frozen at a given value. The status of all pins during a hard power-down is shown in Table 25. Table 25.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 9.6.3 Standby mode The Standby mode is immediately entered when the Control register StandBy bit is set. All internal current sinks, including the internal digital clock buffer are switched off. However, the oscillator buffer is not switched off. The digital input buffers are not separated by the input pads, keeping their functionality and the digital output pins do not change their state.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 9.7.3 Initialization phase The initialization phase automatically follows the reset phase and takes 128 clock cycles. During the initializing phase the content of the EEPROM blocks 1 and 2 is copied into the register subaddresses 10h to 2Fh (see Section 9.2.2 on page 13). Remark: During the production test, the CLRC632 is initialized with default configuration values. This reduces the microprocessor’s configuration time to a minimum. 9.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution If an external clock source is used, the clock signal must be applied to pin OSCIN. In this case, be very careful in optimizing clock duty cycle and clock jitter. Ensure the clock quality has been verified. It must meet the specifications described in Section 13.4.5 on page 106. Remark: We do not recommend using an external clock source. 9.9 Transmitter pins TX1 and TX2 The signal on pins TX1 and TX2 is the 13.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution Table 27. Pin TX2 configurations TxControl register configuration TX2RFEn FORCE100ASK TX2CW Envelope TX2 signal TX2Inv 0 X X X X LOW 1 0 0 0 0 13.56 MHz carrier frequency modulated 1 0 0 0 1 13.56 MHz carrier frequency 1 0 0 1 0 13.56 MHz carrier frequency modulated, 180 phase-shift relative to TX1 1 0 0 1 1 13.56 MHz carrier frequency, 180 phase-shift relative to TX1 1 0 1 0 X 13.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 9.9.3.1 Source resistance table Table 28. TX1 and TX2 source resistance of n-channel driver transistor against GsCfgCW or GsCfgMod MANT = Mantissa; EXP= Exponent. GsCfgCW, GsCfgMod (decimal) EXPGsCfgCW, EXPGsCfgMod (decimal) MANTGsCfgCW, RS(ref) MANTGsCfgMod () (decimal) GsCfgCW, GsCfgMod (decimal) EXPGsCfgCW, EXPGsCfgMod (decimal) MANTGsCfgCW, MANTGsCfgMod (decimal) RS(ref) () 0 0 0 - 24 1 8 0.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 9.9.3.2 Calculating the relative source resistance The reference source resistance RS(ref) can be calculated using Equation 6. 1 R S ref = ------------------------------------------------------------------------------EXP GsCfgCW 77 MANT GsCfgCW ----- 40 (6) The reference source resistance (RS(ref)) during the modulation phase can be calculated using ModConductance register’s GsCfgMod[5:0]. 9.9.3.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution The quadrature demodulator uses two different clocks (Q-clock and I-clock) with a phase-shift of 90 between them. Both resulting subcarrier signals are amplified, filtered and forwarded to the correlation circuitry. The correlation results are evaluated, digitized and then passed to the digital circuitry. Various adjustments can be made to obtain optimum performance for all processing units. 9.10.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution Automatic calibration can be set-up to execute at the end of each Transceive command if bit ClkQCalib = logic 0. Setting bit ClkQCalib = logic 1 disables all automatic calibrations except after the reset sequence. Automatic calibration can also be triggered by the software when bit ClkQCalib has a logic 0 to logic 1 transition.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 9.10.2.3 Correlation circuitry The correlation circuitry calculates the degree of matching between the received and an expected signal. The output is a measure of the amplitude of the expected signal in the received signal. This is done for both, the Q and I-channels. The correlator provides two outputs for each of the two input channels, resulting in a total of four output signals.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution Remark: Pin MFIN can only be accessed at 106 kBd based on ISO/IEC 14443 A. The Manchester signal and the Manchester signal with subcarrier can only be accessed on pin MFOUT at 106 kBd based on ISO/IEC 14443 A. 9.11.1 Serial signal switch block diagram Figure 14 shows the serial signal switches. Three different switches are implemented in the serial signal switch enabling the CLRC632 to be used in different configurations.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution Table 30. DecoderSource[1:0] values See Table 96 on page 67 for additional information. Number DecoderSource Input signal to decoder [1:0] 0 00 constant 0 1 01 output of the analog part. This is the default configuration 2 10 direct connection to pin MFIN; expects an 847.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution Table 33.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 9.13 ISO/IEC 14443 B communication scheme The international standard ISO/IEC 14443 covers two communication schemes; ISO/IEC 14443 A and ISO/IEC 14443 B. The CLRC632 reader IC fully supports both ISO/IEC 14443 variants. Table 35 describes the registers and flags covered by the ISO/IEC 14443 B communication protocol. Table 35.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 9.14 MIFARE authentication and Crypto1 The security algorithm used in the MIFARE products is called Crypto1. It is based on a proprietary stream cipher with a 48-bit key length. To access data on MIFARE cards, knowledge of the key format is needed. The correct key must be available in the CLRC632 to enable successful card authentication and access to the card’s data stored in the EEPROM.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 9.14.2 Authentication procedure The Crypto1 security algorithm enables authentication of MIFARE cards. To obtain valid authentication, the correct key has to be available in the key buffer of the CLRC632. This can be ensured as follows: 1. Load the internal key buffer by using the LoadKeyE2 (see Section 11.7.1 on page 97) or the LoadKey (see Section 11.7.2 on page 97) commands. 2. Start the Authent1 command (see Section 11.7.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution Table 37. Multiplexed address bus: assembling the register address Multiplexed address bus type UsePage Select Register address Paging mode 1 PageSelect2 PageSelect1 PageSelect0 AD2 AD1 AD0 Linear addressing 0 AD5 AD3 AD2 AD1 AD0 AD4 10.2 Register bit behavior Bits and flags for different registers behave differently, depending on their functions. In principle, bits with same behavior are grouped in common registers.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 10.3 Register overview Table 39.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution Table 39.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 10.4 CLRC632 register flags overview Table 40.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution Table 40.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution Table 40.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 10.5 Register descriptions 10.5.1 Page 0: Command and status 10.5.1.1 Page register Selects the page register. Table 41. Page register (address: 00h, 08h, 10h, 18h, 20h, 28h, 30h, 38h) reset value: 1000 0000b, 80h bit allocation Bit 10.5.1.2 7 6 5 4 Symbol UsePageSelect 0000 Access R/W R/W Table 42.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 10.5.1.3 FIFOData register Input and output of the 64 byte FIFO buffer. Table 45. FIFOData register (address: 02h) reset value: xxxx xxxxb, 05h bit allocation Bit 7 5 4 3 Symbol FIFOData[7:0] Access D Table 46. 10.5.1.4 6 2 1 0 FIFOData register bit descriptions Bit Symbol Description 7 to 0 FIFOData[7:0] data input and output port for the internal 64-byte FIFO buffer.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution Table 48.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 10.5.1.6 SecondaryStatus register Various secondary status flags. Table 51. SecondaryStatus register (address: 05h) reset value: 01100 000b, 60h bit allocation Bit 7 6 5 Symbol TRunning E2Ready CRCReady 00 RxLastBits[2:0] Access R R R R R Table 52.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 10.5.1.8 InterruptRq register Interrupt request flags. Table 55. InterruptRq register (address: 07h) reset value: 0000 0000b, 00h bit allocation Bit 7 6 5 4 3 Symbol SetIRq 0 TimerIRq TxIRq RxIRq Access W R/W D D D Table 56.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 10.5.2 Page 1: Control and status 10.5.2.1 Page register Selects the page register; see Section 10.5.1.1 “Page register” on page 50. 10.5.2.2 Control register Various control flags, for timer, power saving, etc. Table 57. Control register (address: 09h) reset value: 0000 0000b, 00h bit allocation Bit 7 5 4 Symbol 00 StandBy Access R/W D Table 58. 10.5.2.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution Table 60. Bit Symbol Value Description 5 AccessErr 1 set when the access rights to the EEPROM are violated 0 set when an EEPROM related command starts 4 FIFOOvfl 1 set when the microprocessor or CLRC632 internal state machine (e.g.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 10.5.2.5 TimerValue register Value of the timer. Table 63. TimerValue register (address: 0Ch) reset value: xxxx xxxxb, xxh bit allocation Bit 7 5 4 3 Symbol TimerValue[7:0] Access R Table 64. 10.5.2.6 6 2 1 0 TimerValue register bit descriptions Bit Symbol Description 7 to 0 TimerValue[7:0] this register shows the timer counter value CRCResultLSB register LSB of the CRC coprocessor register. Table 65.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 10.5.2.8 BitFraming register Adjustments for bit oriented frames. Table 69. BitFraming register (address: 0Fh) reset value: 0000 0000b, 00h bit allocation Bit 7 Symbol 0 RxAlign[2:0] 0 TxLastBits[2:0] Access R/W D R/W D Table 70.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 10.5.3 Page 2: Transmitter and control 10.5.3.1 Page register Selects the page register; see Section 10.5.1.1 “Page register” on page 50. 10.5.3.2 TxControl register Controls the logical behavior of the antenna pin TX1 and TX2. Table 71. TxControl register (address: 11h) reset value: 0101 1000b, 58h bit allocation Bit 7 Symbol 0 Access R/W Table 72.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 10.5.3.3 CwConductance register Selects the conductance of the antenna driver pins TX1 and TX2. Table 73. CwConductance register (address: 12h) reset value: 0011 1111b, 3Fh bit allocation Bit 7 6 Symbol Bit 4 00 Access Table 74.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 10.5.3.5 CoderControl register Sets the clock rate and the coding mode. Table 77. CoderControl register (address: 14h) reset value: 0001 1001b, 19h bit allocation Bit 7 6 Symbol SendOnePulse 0 CoderRate[2:0] TxCoding[2:0] Access R/W R/W R/W R/W Table 78. 3 2 1 0 CoderControl register bit descriptions Symbol Value Description 7 SendOnePulse 1 forced ISO/IEC 15693 modulation.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 10.5.3.6 ModWidth register Selects the pulse-modulation width. Table 79. ModWidth register (address: 15h) reset value: 0001 0011b, 13h bit allocation Bit 10.5.3.7 7 6 3 2 ModWidth[7:0] Access R/W Table 80.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 10.5.3.8 TypeBFraming Defines the framing for ISO/IEC 14443 B communication. Table 83. TypeBFraming register (address: 17h) reset value: 0011 1011b, 3Bh bit allocation Bit 7 Symbol NoTxSOF Access R/W Table 84.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 10.5.4 Page 3: Receiver and decoder control 10.5.4.1 Page register Selects the page register; see Section 10.5.1.1 “Page register” on page 50. 10.5.4.2 RxControl1 register Controls receiver operation. Table 85.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 10.5.4.3 DecoderControl register Controls decoder operation. Table 87. Bit DecoderControl register (address: 1Ah) reset value: 0000 1000b, 08h bit allocation 7 6 Symbol 0 Access R/W Table 88.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 10.5.4.5 RxThreshold register Selects thresholds for the bit decoder. Table 91. RxThreshold register (address: 1Ch) reset value: 1111 1111b, FFh bit allocation Bit 7 5 4 3 2 1 Symbol MinLevel[3:0] CollLevel[3:0] Access R/W R/W Table 92. 10.5.4.6 6 0 RxThreshold register bit descriptions Bit Symbol Description 7 to 4 MinLevel[3:0] the minimum signal strength the decoder will accept.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 10.5.4.7 RxControl2 register Controls decoder behavior and defines the input source for the receiver. Table 95. RxControl2 register (address: 1Eh) reset value: 0100 0001b, 41h bit allocation Bit 7 6 Symbol RcvClkSelI RxAutoPD 0000 DecoderSource[1:0] Access R/W R/W R/W R/W Table 96.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 10.5.5 Page 4: RF Timing and channel redundancy 10.5.5.1 Page register Selects the page register; see Section 10.5.1.1 “Page register” on page 50. 10.5.5.2 RxWait register Selects the time interval after transmission, before the receiver starts. Table 99. RxWait register (address: 21h) reset value: 0000 0101b, 06h bit allocation Bit 7 6 5 4 3 Symbol RxWait[7:0] Access R/W 2 1 0 Table 100.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution Table 102. ChannelRedundancy bit descriptions …continued Bit Symbol Value Function 1 ParityOdd 1 odd parity is generated or expected[1] 0 even parity is generated or expected 1 a parity bit is inserted in the transmitted data stream after each byte and expected in the received data stream after each byte (MIFARE, ISO/IEC 14443 A) 0 no parity bit is inserted or expected (ISO/IEC 14443 B) 0 [1] 10.5.5.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution Table 108. TimeSlotPeriod register bit descriptions 10.5.5.7 Bit Symbol Description 7 to 0 TimeSlotPeriod[7:0] defines the time between automatically transmitted frames. To send a Quit frame using the I-CODE1 protocol it is necessary to relate to the beginning of the command frame. The TimeSlotPeriod starts at the end of the command transmission. See Section 9.5.1.5 on page 26 for additional information.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 10.5.6 Page 5: FIFO, timer and IRQ pin configuration 10.5.6.1 Page register Selects the page register; see Section 10.5.1.1 “Page register” on page 50. 10.5.6.2 FIFOLevel register Defines the levels for FIFO underflow and overflow warning. Table 112. FIFOLevel register (address: 29h) reset value: 0000 1000b, 08h bit allocation Bit 7 6 Symbol 5 4 00 Access 3 2 1 0 WaterLevel[5:0] R/W R/W R/W Table 113.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 10.5.6.4 TimerControl register Selects start and stop conditions for the timer. Table 116. TimerControl register (address: 2Bh) reset value: 0000 0110b, 06h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 0000 TStopRxEnd TStopRxBegin TStartTxEnd TStartTxBegin Access R/W R/W R/W R/W R/W Table 117.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 10.5.6.6 IRQPinConfig register Configures the output stage for pin IRQ. Table 120. IRQPinConfig register (address: 2Dh) reset value: 0000 0010b, 02h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 000000 IRQInv IRQPushPull Access R/W R/W R/W Table 121. IRQPinConfig register bit descriptions Bit Symbol Value Description 7 to 2 000000 - these values must not be changed 1 IRQInv 0 10.5.6.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 10.5.8 Page 7: Test control 10.5.8.1 Page register Selects the page register; see Section 10.5.1.1 “Page register” on page 50. 10.5.8.2 Reserved register 39h Table 125. Reserved register (address: 39h) reset value: xxxx xxxxb, xxh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol x x x x x x x x Access W W W W W W W W Remark: This register is reserved for future use. 10.5.8.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 10.5.8.4 Reserved register 3Bh Table 128. Reserved register (address: 3Bh) reset value: xxxx xxxxb, xxh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol x x x x x x x x Access W W W W W W W W Remark: This register is reserved for future use. 10.5.8.5 Reserved register 3Ch Table 129.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 10.5.8.7 Reserved registers 3Eh, 3Fh Table 132. Reserved register (address: 3Eh, 3Fh) reset value: xxxx xxxxb, xxh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol x x x x x x x x Access W W W W W W W W Remark: This register is reserved for future use. 11. CLRC632 command set CLRC632 operation is determined by an internal state machine capable of performing a command set.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution Table 133. CLRC632 commands overview …continued Command Value Action FIFO communication Arguments and data sent Data received Transceive[1] 1Eh data stream transmits data from FIFO buffer to the card and automatically activates the receiver after transmission. The receiver waits until the time defined in the RxWait register has elapsed before starting. See Section 11.2.3 on page 85.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 11.1.1 Basic states 11.1.2 StartUp command 3Fh Table 134. StartUp command 3Fh Command Value Action Arguments and data Returned data StartUp 3Fh runs the reset and initialization phase - - Remark: This command can only be activated by a Power-On or Hard reset. The StartUp command runs the reset and initialization phases. It does not need or return, any data.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 11.2 Commands for ISO/IEC 14443 A card communication The CLRC632 is a fully ISO/IEC 14443 A, ISO/IEC 14443 B, ISO/IEC 15693 and I-CODE1 compliant reader IC. This enables the command set to be more flexible and generalized when compared to dedicated MIFARE or I-CODE1 reader ICs. Section 11.2.1 to Section 11.2.5 describe the command set for ISO/IEC 14443 A card communication and related communication protocols. 11.2.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 11.2.1.2 RF channel redundancy and framing Each ISO/IEC 14443 A transmitted frame consists of a Start Of Frame (SOF) pattern, followed by the data stream and is closed by an End Of Frame (EOF) pattern. These different phases of the transmission sequence can be monitored using the PrimaryStatus register ModemState[2:0] bit; see Section 11.2.4 on page 85.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution TxLastBits[2:0] TxLastBits = 0 FIFOLength[6:0] 01h 00h FIFO empty TxData 7 0 7 0 7 check FIFO empty accept further data 001aak619 Fig 17. Timing for transmitting byte oriented frames As long as the internal accept further data signal is logic 1, further data can be written to the FIFO buffer. The CLRC632 appends this data to the data stream transmitted using the RF interface.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution Figure 18 also shows write access to the FIFOData register just before the FIFO buffer’s status is checked. This leads to FIFO empty state being held LOW which keeps the accept further data active. The new byte written to the FIFO buffer is transmitted using the RF interface. Accept further data is only changed by the check FIFO empty function.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution If an EOF pattern is detected or the signal strength falls below the RxThreshold register MinLevel[3:0] bits setting, both the receiver and the decoder stop. Then the Idle command is entered and an appropriate response for the microprocessor is generated (interrupt request activated, status flags set). When the ChannelRedundancy register bit RxCRCEn is set, a CRC block is expected.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution Table 139.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 11.2.3 Transceive command 1Eh Table 141. Transceive command 1Eh Command Value Action Arguments and data Transceive 1Eh transmits data from FIFO buffer to the card data stream and then automatically activates the receiver Returned data data stream The Transceive command first executes the Transmit command (see Section 11.2.1 on page 79) and then starts the Receive command (see Section 11.2.2 on page 82).
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 11.2.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 11.3 I-CODE1 and ISO/IEC 15693 label communication commands The CLRC632 is a fully ISO/IEC 14443 A, ISO/IEC 14443 B, ISO/IEC 15693 and I-CODE1 compliant reader IC. This enables the command set to be more flexible and generalized when compared to dedicated MIFARE or I-CODE1 reader ICs. Section 11.3.1 to Section 11.3.5 give an overview of the command set for I-CODE1 and ISO/IEC 15693 card communication and related communication protocols.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 11.3.1.2 RF channel redundancy and framing Each transmitted ISO/IEC 15693 frame consists of a Start Of Frame (SOF) pattern, followed by the data stream and is closed by an End Of Frame (EOF) pattern. All I-CODE1 command frames consists of a start pulse followed by the data stream. The I-CODE1 commands have a fixed length and do not need an EOF.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution Remark: This command may be used for test purposes only, since there is no timing relation to the Transmit command. 11.3.2.1 Using the Receive command After starting the Receive command the internal state machine decrements the RxWait register value on every bit-clock. The analog receiver circuitry is prepared and activated from 3 down to 1.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution To distinguish between a 1-bit or 0-bit from a bit-collision, the RxThreshold register’s CollLevel[3:0] value is used. If the amplitude of the half-bit with smaller amplitude is larger than defined by CollLevel[3:0], a bit-collision is flagged by setting the CollErr error flag. The receiver continues receiving the incoming data stream independently from the detected collision.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 11.3.3 Transceive command 1Eh Table 147. Transceive command 1Eh Command Value Action Arguments and data Returned data Transceive 1Eh transmits data from FIFO buffer to the label and then activates the receiver data stream data stream The Transceive command first executes the Transmit command (see Section 11.2.1 on page 79) and then starts the Receive command (see Section 11.2.2 on page 82).
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 11.3.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 11.4 EEPROM commands 11.4.1 WriteE2 command 01h Table 149. WriteE2 command 01h Command Value Action FIFO Arguments and data WriteE2 01h get data from FIFO buffer and write it to the EEPROM Returned data start address LSB - start address MSB - data byte stream - The WriteE2 command interprets the first two bytes in the FIFO buffer as the EEPROM start byte address.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 11.4.1.2 Timing diagram Figure 22 shows programming five bytes into the EEPROM. tprog,del NWR data write E2 addr LSB addr byte 0 MSB byte 1 byte 2 byte 3 Idle command byte 4 WriteE2 command active EEPROM programming tprog tprog tprog programming byte 0 programming byte 1, byte 2 and byte 3 programming byte 4 E2Ready TxIRq 001aak623 Fig 22.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 11.4.2 ReadE2 command 03h Table 150. ReadE2 command 03h Command Value Action Arguments Returned data ReadE2 03h start address LSB data bytes reads EEPROM data and stores it in the FIFO buffer start address MSB number of data bytes The ReadE2 command interprets the first two bytes stored in the FIFO buffer as the EEPROM starting byte address. The next byte specifies the number of data bytes returned.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 11.5.1.2 Relevant LoadConfig command error flags Valid EEPROM starting byte addresses are between 10h and 60h. Copying from block 8h to 1Fh (keys) is restricted. Reading from these addresses sets the flag AccessErr = logic 1. Addresses above 1FFh are taken as modulo 200h; see Section 9.2 on page 12 for the EEPROM memory organization. 11.5.2 CalcCRC command 12h Table 152.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 11.6 Error handling during command execution If an error is detected during command execution, the PrimaryStatus register Err flag is set. The microprocessor can evaluate the status flags in the ErrorFlag register to get information about the cause of the error. Table 154.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution The LoadKey command interprets the first twelve bytes it finds in the FIFO buffer as the key when stored in the correct key format as described in Section 9.2.3.1 “Key format” on page 18. When the twelve argument bytes are available in the FIFO buffer they are checked and, if valid, are copied into the key buffer.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 11.7.4.1 Authent2 command effects If the Authent2 command is successful, the authenticity of card and the CLRC632 are proved. This automatically sets the Crypto1On control bit. When bit Crypto1On = logic 1, all further card communication is encrypted using the Crypto1 security algorithm. If the Authent2 command fails, bit Crypto1On is cleared (Crypto1On = logic 0).
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 13.2 Current consumption Table 161.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution Pin RSTPD has Schmitt trigger CMOS characteristics. In addition, it is internally filtered by a RC low-pass filter which causes a propagation delay on the reset signal. Table 164. RSTPD input pin characteristics Symbol Parameter Conditions ILI input leakage current Vth threshold voltage tPD Min Typ Max Unit 1.0 - A +1.0 positive-going threshold; CMOS = VDDD < 3.6 V 0.65VDDD - 0.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution Table 167. Antenna driver output pin characteristics Symbol Parameter Conditions Min Typ VOH HIGH-level output voltage VDD(TVDD) = 5.0 V; IOL = 20 mA - 4.97 - VDD(TVDD) = 5.0 V; IOL = 100 mA - 4.85 - V VOL LOW-level output voltage VDD(TVDD) = 5.0 V; IOL = 20 mA - 30 - mV VDD(TVDD) = 5.0 V; IOL = 100 mA - 150 - mV output current transmitter; continuous wave; peak-to-peak - - 200 mA IO Max Unit V 13.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution tLHLL ALE tSLRWL tRWHSH NCS tLLRWL tRWHRWL tRWLRWH tRWHRWL NWR NRD tAVLL D0 to D7 tWLQV tRLDV tLLAX A0 to A2 tWHDX tRHDZ D0 to D7 Multiplexed address bus tAVRWL A0 to A2 tWHAX A0 to A2 Separated address bus 001aaj638 Fig 23. Separate read/write strobe timing diagram Remark: The signal ALE is not relevant for separate address/data bus and the multiplexed addresses on the data bus do not care.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution Table 169.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution Table 170.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 13.4.4 SPI timing Table 171.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 14. EEPROM characteristics The EEPROM size is 32 16 8 = 4096 bit. Table 173. EEPROM characteristics Symbol Parameter Conditions Min Nendu(W_ER) write or erase endurance erase/write cycles Tamb 55 C Typ Max Unit 100.000 - - Hz tret retention time 10 - - year ter erase time - - 2.9 ms ta(W) write access time - - 2.9 ms 15. Application information 15.1 Typical application 15.1.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 15.1.2 Circuit description The matching circuit consists of an EMC low-pass filter (L0 and C0), matching circuitry (C1 and C2), a receiver circuit (R1, R2, C3 and C4) and the antenna itself. Refer to the following application notes for more detailed information about designing and tuning an antenna. • MICORE reader IC family; Directly Matched Antenna Design Ref. 1 • MIFARE (14443 A) 13.56 MHz RFID Proximity Antennas Ref. 2. 15.1.2.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution It is recommended to use the internally generated VMID potential as the input potential for pin RX. This VMID DC voltage level has to be coupled to pin RX using resistor (R2). To provide a stable DC reference voltage, a capacitor (C4) must be connected between VMID and ground. The AC voltage divider of R1 + C3 and R2 has to be designed taking in to account the AC voltage limits on pin RX.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 15.2 Test signals The CLRC632 allows different kinds of signal measurements. These measurements can be used to check the internally generated and received signals using the serial signal switch as described in Section 9.11 on page 37.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution (1) (2) (3) 10 μs per division 001aak626 (1) MFOUTSelect[2:0] = 3; serial data stream; 2 V per division. (2) MFOUTSelect[2:0] = 2; serial data stream; 2 V per division. (3) RFOut; 1 V per division. Fig 28. TX control signals 15.2.1.2 RX control Figure 29 shows an example of ISO/IEC 14443 A communication which represents the beginning of a card’s answer to a request signal.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution (1) (2) (3) 10 μs per division 001aak627 (1) RFOut; 1 V per division. (2) MFOUTSelect[2:0] = 4; Manchester with subcarrier; 2 V per division. (3) MFOUTSelect[2:0] = 5; Manchester; 2 V per division. Fig 29. RX control signals 15.2.2 Analog test signals The analog test signals can be routed to pin AUX by selecting them using the TestAnaSelect register TestAnaOutSel[4:0] bits. Table 175.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution Table 175. Analog test signal selection …continued Value Signal Name Description B VEvalR evaluation signal from the right half-bit C VTemp temperature voltage derived from band gap D reserved reserved for future use E reserved reserved for future use F reserved reserved for future use 15.2.3 Digital test signals Digital test signals can be routed to pin MFOUT by setting bit SignalToMFOUT = logic 1.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution Signals VEvalR and VEvalL show the evaluation of the signal’s right and left half-bit. Finally, the digital test signal s_data shows the received data. This is then sent to the internal digital circuit and s_valid which indicates the received data stream is valid. RX reference VRxAmpQ VCorrDQ VCorrNQ VEvalR VEvalL s_data s_valid 50 μs per division 001aak628 Fig 30. ISO/IEC 14443 A receiving path Q-clock 15.2.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution receiving path Q-Clock VRxAmpQ VCorrDQ VCorrNQ VEvalR VEvalL s_data 50 μs per division s_valid 500 μs per division 001aak629 Fig 31. I-CODE1 receiving path Q-clock CLRC632 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.7 — 27 February 2014 073937 © NXP Semiconductors N.V. 2014. All rights reserved.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 16. Package outline SO32: plastic small outline package; 32 leads; body width 7.5 mm SOT287-1 D E A X c y HE v M A Z 17 32 Q A2 A (A 3) A1 pin 1 index θ Lp L 16 1 0 detail X w M bp e 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.27 0.18 20.7 20.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 17. Abbreviations Table 177.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 19. Revision history Table 178. Revision history Document ID Release date CLRC632 v. 3.7 20140227 Modifications: • CLRC632_35 Modifications: CLRC632_34 Modifications: • • Supersedes Product data sheet - CLRC632 v. 3.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 20. Legal information 20.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 22. Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution value: 0011 1111b, 3Fh bit allocation . . . . . . . .62 Table 82. ModWidthSOF register bit descriptions . . . . . .62 Table 83. TypeBFraming register (address: 17h) reset value: 0011 1011b, 3Bh bit allocation . . . . . . .63 Table 84. TypeBFraming register bit descriptions . . . . . .63 Table 85. RxControl1 register (address: 19h) reset value: 0111 0011b, 73h bit allocation . . . . . . . . . . . . .64 Table 86.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 Table 166. Digital output pin characteristics . . . . . . . . . .101 Table 167. Antenna driver output pin characteristics . . .102 Table 168. Timing specification for separate read/write strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 Table 169. Common read/write strobe timing specification . . . . . . . . . . . . . . . . . . . . . . . . . .
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 23. Figures Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. Fig 15. Fig 16. Fig 17. Fig 18. Fig 19. Fig 20. Fig 21. Fig 22. Fig 23. Fig 24. Fig 25. Fig 26. Fig 27. Fig 28. Fig 29. Fig 30. Fig 31. Fig 32. CLRC632 block diagram . . . . . . . . . . . . . . . . . . . .4 CLRC632 pin configuration . . . . . . . . . . . . . . . . . .
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 24. Contents 1 2 3 3.1 4 5 6 7 8 8.1 9 9.1 9.1.1 9.1.2 9.1.3 9.1.3.1 9.1.3.2 9.1.3.3 9.1.4 9.1.4.1 9.1.4.2 9.2 9.2.1 9.2.2 9.2.2.1 9.2.2.2 9.2.2.3 9.2.2.4 9.2.3 9.2.3.1 9.2.3.2 9.3 9.3.1 9.3.1.1 9.3.2 9.3.3 9.3.4 9.4 9.4.1 9.4.2 9.4.2.1 9.4.2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . .
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 9.13 ISO/IEC 14443 B communication scheme . . . 9.14 MIFARE authentication and Crypto1 . . . . . . . 9.14.1 Crypto1 key handling . . . . . . . . . . . . . . . . . . . 9.14.2 Authentication procedure . . . . . . . . . . . . . . . . 10 CLRC632 registers. . . . . . . . . . . . . . . . . . . . . . 10.1 Register addressing modes . . . . . . . . . . . . . . 10.1.1 Page registers . . . . . . . . . . . . . . . . . . . . . . . . 10.1.
CLRC632 NXP Semiconductors Standard multi-protocol reader solution 11.2.4 11.2.5 11.3 States of the card communication. . . . . . . . . . 85 Card communication state diagram . . . . . . . . 86 I-CODE1 and ISO/IEC 15693 label communication commands . . . . . . . . . . . . . . . 87 11.3.1 Transmit command 1Ah . . . . . . . . . . . . . . . . . 87 11.3.1.1 Using the Transmit command. . . . . . . . . . . . . 87 11.3.1.2 RF channel redundancy and framing . . . . . . . 88 11.3.1.