56F801 Data Sheet Preliminary Technical Data 56F800 16-bit Digital Signal Controllers DSP56F801 Rev. 17 09/2007 freescale.
Document Revision History Version History Rev. 17 Description of Change Added revision history. Added this text to footnote 2 in Table 3-8: “However, the high pulse width does not have to be any particular percent of the low pulse width.
56F801 General Description • Up to 30 MIPS operation at 60MHz core frequency • 8K × 16-bit words (16KB) Program Flash • Up to 40 MIPS operation at 80MHz core frequency • 1K × 16-bit words (2KB) Program RAM • DSP and MCU functionality in a unified, C-efficient architecture • 2K × 16-bit words (4KB) Data Flash • MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes • 2K × 16-bit words (4KB) Boot Flash • Hardware DO and REP loops • JTA
Part 1 Overview 1.1 56F801 Features 1.1.1 • • • • • • • • • • • • • • 1.1.
6F801 Description • • • • • • • 1.1.
A key application-specific feature of the 56F801 is the inclusion of a Pulse Width Modulator (PWM) module. This modules incorporates six complementary, individually programmable PWM signal outputs to enhance motor control functionality. Complementary operation permits programmable dead-time insertion, and separate top and bottom output polarity control. The up-counter value is programmable to support a continuously variable PWM frequency.
Product Documentation 1.4 Product Documentation The four documents listed in Table 1-1 are required for a complete description and proper design with the 56F801. Documentation is available from local Freescale distributors, Freescale semiconductor sales offices, Freescale Literature Distribution Centers, or online at www.freescale.com.
Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F801 are organized into functional groups, as shown in Table 2-1 and as illustrated in Figure 2-1. In Table 2-2 through Table 2-12, each table row describes the signal or signals present on a pin.
Introduction Power Port Ground Port Power Port Ground Port VDD 4 VSS 5* VDDA 1 VSSA 1 Other Supply Port VCAPC PLL and Clock or GPIO EXTAL (GPIOB2) XTAL (GPIOB3) PWMA0-5 2 6 1 FAULTA0 1 SCLK (GPIOB4) 1 MOSI (GPIOB5) 1 MISO (GPIOB6) 1 SS (GPIOB7) 1 TXD0 (GPIOB0) 1 RXD0 (GPIOB1) 8 ANA0-7 1 VREF 3 TD0-2 (GPIOA0-2) 1 IRQA 1 RESET 1 1 56F801 TCK TMS TDI JTAG/OnCE™ Port TDO TRST DE SPI Port or GPIO SCI0 Port or GPIO ADCA Port Quad Timer D or GPIO 1 1 1 1 Interrupt/
2.2 Power and Ground Signals Table 2-2 Power Inputs No. of Pins Signal Name Signal Description 4 VDD Power—These pins provide power to the internal structures of the chip, and should all be attached to VDD. 1 VDDA Analog Power—This pin is a dedicated power pin for the analog portion of the chip and should be connected to a low noise 3.3V supply. Table 2-3 Grounds No.
Interrupt and Program Control Signals Table 2-5 PLL and Clock (Continued) No. of Pins Signal Name Signal Type State During Reset 1 XTAL Output Chipdriven Signal Description Crystal Oscillator Output—This output should be connected to an 8MHz external crystal or ceramic resonator. For more information, please refer to Section 3.5. This pin can also be connected to an external clock source. For more information, please refer to Section 3.5.3.
2.6 Serial Peripheral Interface (SPI) Signals Table 2-8 Serial Peripheral Interface (SPI) Signals No. of Pins Signal Name Signal Type State During Reset 1 MISO Input/Output Input SPI Master In/Slave Out (MISO)—This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected.
Serial Communications Interface (SCI) Signals 2.7 Serial Communications Interface (SCI) Signals Table 2-9 Serial Communications Interface (SCI0) Signals No. of Pins Signal Name Signal Type State During Reset 1 TXD0 Output Input Transmit Data (TXD0)—SCI0 transmit data output GPIOB0 Input/Output Input Port B GPIO—This pin is a General Purpose I/O (GPIO) pin that can be individually programmed as an input or output pin. Signal Description After reset, the default state is SCI output.
2.10 JTAG/OnCE Table 2-12 JTAG/On-Chip Emulation (OnCE) Signals No. of Pins Signal Name Signal Type State During Reset 1 TCK Input (Schmitt) Input, pulled low internally 1 TMS Input (Schmitt) Input, pulled Test Mode Select Input—This input pin is used to sequence the JTAG high internally TAP controller’s state machine. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor.
General Characteristics The 56F801 DC and AC electrical specifications are preliminary and are from design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications will be published after complete characterization and device qualifications have been completed. CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields.
Table 3-3 Thermal Characteristics6 Value Characteristic Comments Symbol Unit Notes 48-pin LQFP Junction to ambient Natural convection Junction to ambient (@1m/sec) RθJA 50.6 °C/W 2 RθJMA 47.4 °C/W 2 Junction to ambient Natural convection Four layer board (2s2p) RθJMA (2s2p) 39.1 °C/W 1,2 Junction to ambient (@1m/sec) Four layer board (2s2p) RθJMA 37.9 °C/W 1,2 Junction to case RθJC 17.3 °C/W 3 Junction to center of case ΨJT 1.
DC Electrical Characteristics 3.2 DC Electrical Characteristics Table 3-4 DC Electrical Characteristics Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF Characteristic Symbol Min Typ Max Unit Input high voltage (XTAL/EXTAL) VIHC 2.25 — 2.75 V Input low voltage (XTAL/EXTAL) VILC 0 — 0.5 V Input high voltage [GPIOB(2:3)]1 VIH[GPIOB(2:3)] 2.0 — 3.6 V Input low voltage [GPIOB(2:3)]1 VIL[GPIOB(2:3)] -0.3 — 0.
Table 3-4 DC Electrical Characteristics (Continued) Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF Characteristic Symbol Min Typ Max Unit Run7 (80MHz operation) — 120 130 mA Run7 (60MHz operation) — 102 111 mA Wait8 — 96 102 mA Stop — 62 70 mA VDD supply current IDDT6 Low Voltage Interrupt, external power supply9 VEIO 2.4 2.7 3.0 V Low Voltage Interrupt, internal power supply10 VEIC 2.0 2.2 2.
AC Electrical Characteristics 160 IDD Digital IDD Analog IDD Total IDD (mA) 120 80 40 0 10 20 30 40 50 60 70 80 Freq. (MHz) Figure 3-1 Maximum Run IDD vs. Frequency (see Note 7. in Table 3-15) 3.3 AC Electrical Characteristics Timing waveforms in Section 3.3 are tested using the VIL and VIH levels specified in the DC Characteristics table. In Figure 3-2 the levels of VIH and VIL for an input signal are shown.
Data2 Valid Data1 Valid Data3 Valid Data2 Data1 Data3 Data Tri-stated Data Invalid State Data Active Data Active Figure 3-3 Signal States 3.4 Flash Memory Characteristics Table 3-5 Flash Memory Truth Table Mode XE1 YE2 SE3 OE4 PROG5 ERASE6 MAS17 NVSTR8 Standby L L L L L L L L Read H H H H L L L L Word Program H H L L H L L H Page Erase H L L L L H L H Mass Erase H L L L L H H H 1. X address enable, all rows are disabled when XE = 0 2.
Flash Memory Characteristics Table 3-7 Flash Timing Parameters Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.
IFREN XADR XE Tadh YADR YE DIN Tads PROG Tnvs Tprog Tpgh NVSTR Tpgs Tnvh Trcv Thv Figure 3-4 Flash Program Cycle IFREN XADR XE YE=SE=OE=MAS1=0 ERASE Tnvs NVSTR Tnvh Terase Trcv Figure 3-5 Flash Erase Cycle 56F801 Technical Data, Rev.
External Clock Operation IFREN XADR XE MAS1 YE=SE=OE=0 ERASE Tnvs NVSTR Tnvh1 Tme Trcv Figure 3-6 Flash Mass Erase Cycle 3.5 External Clock Operation The 56F801 device clock is derived from either 1) an internal crystal oscillator circuit working in conjunction with an external crystal, 2) an external frequency source, or 3) an on-chip relaxation oscillator.
is designed to have no external load capacitors present. As shown in Figure 3-8 no external load capacitors should be used. The 56F80x components internally are modeled as a parallel resonant oscillator circuit to provide a capacitive load on each of the oscillator pins (XTAL and EXTAL) of 10pF to 13pF over temperature and process variations.
External Clock Operation 3.5.3 External Clock Source The recommended method of connecting an external clock is given in Figure 3-9. The external clock source is connected to XTAL and the EXTAL pin is grounded. 56F801 XTAL EXTAL External Clock VSS Figure 3-9 Connecting an External Clock Signal Table 3-8 External Clock Operation Timing Requirements3 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.
compensate for any asynchronous transitions between the two clock signals so that no glitches occur in the resulting master clock to the chip. When changing clocks, the user must ensure that the clock source is not switched until the desired clock is enabled and stable. To compensate for variances in the device manufacturing process, the accuracy of the relaxation oscillator can be incrementally adjusted to within ±0.25% of 8MHz by trimming an internal capacitor.
External Clock Operation 8.2 Output Frequency 8.1 8.0 7.9 7.8 7.7 7.6 -40 -25 -5 15 35 55 75 85 Temperature (oC) Figure 3-11 Typical Relaxation Oscillator Frequency vs. Temperature (Trimmed to 8MHz @ 25oC) 11 10 9 8 7 6 5 0 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 Figure 3-12 Typical Relaxation Oscillator Frequency vs. Trim Value @ 25oC 56F801 Technical Data, Rev.
3.5.5 Phase Locked Loop Timing Table 3-10 PLL Timing Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C Characteristic Symbol Min Typ Max Unit fosc 4 8 10 MHz fout/2 40 — 803 MHz PLL stabilization time4 0o to +85oC tplls — 10 — ms PLL stabilization time4 -40o to 0oC tplls — 100 200 ms External reference crystal frequency for the PLL1 PLL output frequency2 1.
Reset, Stop, Wait, Mode Select, and Interrupt Timing 3.6 Reset, Stop, Wait, Mode Select, and Interrupt Timing Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 5 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.
RESET tRA tRAZ tRDA A0–A15, D0–D15 First Fetch PS, DS, RD, WR First Fetch Figure 3-13 Asynchronous Reset Timing IRQA, IRQB tIRW Figure 3-14 External Interrupt Timing (Negative-Edge-Sensitive) A0–A15, PS, DS, RD, WR First Interrupt Instruction Execution tIDM IRQA, IRQB a) First Interrupt Instruction Execution General Purpose I/O Pin tIG IRQA, IRQB b) General Purpose I/O Figure 3-15 External Level-Sensitive Interrupt Timing 56F801 Technical Data, Rev.
Reset, Stop, Wait, Mode Select, and Interrupt Timing IRQA, IRQB tIRI A0–A15, PS, DS, RD, WR First Interrupt Vector Instruction Fetch Figure 3-16 Interrupt from Wait State Timing tIW IRQA tIF A0–A15, PS, DS, RD, WR First Instruction Fetch Not IRQA Interrupt Vector Figure 3-17 Recovery from Stop State Using Asynchronous Interrupt Timing tIRQ IRQA tII A0–A15 PS, DS, RD, WR First IRQA Interrupt Instruction Fetch Figure 3-18 Recovery from Stop State Using IRQA Interrupt Service 56F801 Technical Da
3.7 Serial Peripheral Interface (SPI) Timing Table 3-12 SPI Timing1 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF Characteristic Symbol Cycle time Master Slave Min Max Unit 50 25 — — ns ns — 25 — — ns ns — 100 — — ns ns 17.6 12.5 — — ns ns 24.1 25 — — ns ns 20 0 — — ns ns 0 2 — — ns ns 4.8 15 ns 3.7 15.2 ns — — 4.5 20.4 ns ns 0 0 — — ns ns — — 11.5 10.0 ns ns — — 9.7 9.
Serial Peripheral Interface (SPI) Timing SS SS is held High on master (Input) tC tR tF tCL SCLK (CPOL = 0) (Output) tF tCH tR tCL SCLK (CPOL = 1) (Output) tDH tCH tDS MISO (Input) MSB in Bits 14–1 tDI MOSI (Output) LSB in tDI(ref) tDV Master MSB out Bits 14–1 Master LSB out tF tR Figure 3-19 SPI Master Timing (CPHA = 0) SS SS is held High on master (Input) tF tC tR tCL SCLK (CPOL = 0) (Output) tCH tF tCL SCLK (CPOL = 1) (Output) tCH MISO (Input) MSB in tDH Bits 14–
SS (Input) tC tF tCL SCLK (CPOL = 0) (Input) tELG tR tCH tELD tCL SCLK (CPOL = 1) (Input) tCH tA MISO (Output) Slave MSB out tDS tR tF tD Bits 14–1 Slave LSB out tDV tDI tDI tDH MOSI (Input) MSB in Bits 14–1 LSB in Figure 3-21 SPI Slave Timing (CPHA = 0) SS (Input) tC tF tCL SCLK (CPOL = 0) (Input) tCH tELG tELD SCLK (CPOL = 1) (Input) tR tDV tCL tR tCH tA MISO (Output) Slave MSB out Bits 14–1 tDV tDS tDH MOSI (Input) MSB in tD tF Bits 14–1 Slave LSB out tDI
Quad Timer Timing 3.8 Quad Timer Timing Table 3-13 Timer Timing1, 2 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF Characteristic Symbol Min Max Unit PIN 4T+6 — ns Timer input high/low period PINHL 2T+3 — ns Timer output period POUT 2T — ns POUTHL 1T — ns Timer input period Timer output high/low period 1. In the formulas listed, T = clock cycle. For 80MHz operation, T = 12.5ns. 2. Parameters listed are guaranteed by design.
RXD SCI receive data pin (Input) RXDPW Figure 3-24 RXD Pulse Width TXD SCI receive data pin (Input) TXDPW Figure 3-25 TXD Pulse Width 3.10 Analog-to-Digital Converter (ADC) Characteristics Table 3-15 ADC Characteristics Characteristic Symbol Min Typ Max Unit VADCIN 01 — VREF2 V Resolution RES 12 — 12 Bits Integral Non-Linearity3 INL — +/- 4 +/- 5 LSB4 Differential Non-Linearity DNL — +/- 0.
Analog-to-Digital Converter (ADC) Characteristics Table 3-15 ADC Characteristics (Continued) Characteristic Symbol Min Typ Max Unit THD 55 60 — dB Signal-to-Noise plus Distortion5 SINAD 54 56 — dB Effective Number of Bits5 ENOB 8.5 9.5 — bit Spurious Free Dynamic Range5 SFDR 60 65 — dB Bandwidth BW — 100 — KHz ADC Quiescent Current (both ADCs) IADC — 50 — mA VREF Quiescent Current (both ADCs) IVREF — 12 16.5 mA Total Harmonic Distortion5 1.
3.11 JTAG Timing Table 3-16 JTAG Timing 1, 3 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF Characteristic Symbol Min Max Unit TCK frequency of operation2 fOP DC 10 MHz TCK cycle time tCY 100 — ns TCK clock pulse width tPW 50 — ns TMS, TDI data setup time tDS 0.4 — ns TMS, TDI data hold time tDH 1.2 — ns TCK low to TDO data valid tDV — 26.6 ns TCK low to TDO tri-state tTS — 23.
JTAG Timing TCK (Input) tDS TDI TMS (Input) tDH Input Data Valid tDV TDO (Output) Output Data Valid tTS TDO (Output) tDV TDO (Output) Output Data Valid Figure 3-28 Test Access Port Timing Diagram TRST (Input) tTRST Figure 3-29 TRST Timing Diagram DE tDE Figure 3-30 OnCE—Debug Event 56F801 Technical Data, Rev.
Part 4 Packaging 4.1 Package and Pin-Out Information 56F801 ANA5 ANA6 ANA7 ORIENTATION MARK TDO ANA4 PIN 37 TD1 TD2 PWMA0 VCAPC1 VDD VSS PWMA1 PWMA2 PWMA3 PWMA4 PWMA5 This section contains package and pin-out information for the 48-pin LQFP configuration of the 56F801.
Package and Pin-Out Information 56F801 Table 4-1 56F801 Pin Identification by Pin Number Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
4X 0.200 AB T-U Z DETAIL Y A P A1 48 37 1 36 T U B V AE B1 12 25 13 AE V1 24 Z S1 DIM A A1 B B1 C D E F G H J K L M N P R S S1 V V1 W AA T, U, Z S DETAIL Y 4X 0.200 AC T-U Z 0.080 AC G AB AD AC M° BASE METAL TOP & BOTTOM R J 0.250 N MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.170 0.270 1.350 1.450 0.170 0.230 0.500 BSC 0.050 0.150 0.090 0.200 0.500 0.700 0 ° 7° 12 ° REF 0.090 0.160 0.250 BSC 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.
Thermal Design Considerations Part 5 Design Considerations 5.
• Measure the thermal resistance from the junction to where the leads are attached to the case. This definition is approximately equal to a junction to board thermal resistance. • Use the value obtained by the equation (TJ – TT)/PD where TT is the temperature of the package case determined by a thermocouple. The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case.
Electrical Design Considerations • • Bypass the VDD and VSS layers of the PCB with approximately 100 μF, preferably with a high-grade capacitor such as a tantalum capacitor. Because the controller’s output signals have fast rise and fall times, PCB trace lengths should be minimal. Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.
Part 6 Ordering Information Table 6-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor sales office or authorized distributor to determine availability and to order parts. Table 6-1 56F801 Ordering Information Pin Count Ambient Frequency (MHz) Order Number Low Profile Plastic Quad Flat Pack (LQFP) 48 80 DSP56F801FA80 3.0–3.6 V Low Profile Plastic Quad Flat Pack (LQFP) 48 60 DSP56F801FA60 56F801 3.0–3.
Electrical Design Considerations 56F801 Technical Data, Rev.
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