56F803 Data Sheet Preliminary Technical Data 56F800 16-bit Digital Signal Controllers DSP56F803 Rev. 16 09/2007 freescale.
Document Revision History Version History Rev. 16 Description of Change Added revision history. Added this text to footnote 2 in Table 3-8: “However, the high pulse width does not have to be any particular percent of the low pulse width.
56F803 General Description • Up to 40 MIPS at 80MHz core frequency • 6-channel PWM module • DSP and MCU functionality in a unified, C-efficient architecture • Two 4-channel 12-bit ADCs • Quadrature Decoder • Hardware DO and REP loops • CAN 2.0 B module • MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes • Serial Communication Interface (SCI) • Serial Peripheral Interface (SPI) • 31.
Part 1 Overview 1.1 56F803 Features 1.1.1 • • • • • • • • • • • • • • 1.1.
6F803 Description • • • • • • • • • • 1.1.4 • • • • Four General Purpose Quad Timers: Timer A (sharing pins with Quad Dec0), Timers B &C without external pins and Timer D with two pins CAN 2.
software routines that can be used to program the main Program and Data Flash memory areas. Both Program and Data Flash memories can be independently bulk–erased or erased in page sizes of 256 words. The Boot Flash memory can also be either bulk- or page-erased. A key application-specific feature of the 56F803 is the inclusion of a Pulse Width Modulator (PWM) module.
Product Documentation 1.4 Product Documentation The four documents listed in Table 1-1 are required for a complete description and proper design with the 56F803. Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature Distribution Centers, or online at: www.freescale.
Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F803 are organized into functional groups, as shown in Table 2-1 and as illustrated in Figure 2-1. In Table 2-2 through Table 2-17, each table row describes the signal or signals present on a pin.
Introduction Power Port VDD 6 Ground Port VSS 6* Power Port VDDA 1 Ground Port VSSA 1 Other Supply Ports VCAPC PLL and Clock EXTAL XTAL CLKO A0-A5 External Address Bus or GPIO External Data Bus A6-7 (GPIOE2-E3) A8-15 (GPIOA0-A7) D0–D15 PS DS External Bus Control RD WR PHASEA0 (TA0) Quadrature Decoder or Quad Timer A PHASEB0 (TA1) INDEX0 (TA2) HOME0 (TA3) 6 3 2 3 TCK JTAG/OnCE™ Port TDI TDO TRST DE ISA0-2 FAULTA0-2 PWMA Port 1 1 56F803 1 1 6 2 8 16 1 1 1 1 1 SCLK (GPIO
2.2 Power and Ground Signals Table 2-2 Power Inputs No. of Pins Signal Name Signal Description 6 VDD Power—These pins provide power to the internal structures of the chip, and should all be attached to VDD. 1 VDDA Analog Power—This pin is a dedicated power pin for the analog portion of the chip and should be connected to a low noise 3.3V supply. Table 2-3 Grounds No.
Clock and Phase Locked Loop Signals 2.3 Clock and Phase Locked Loop Signals Table 2-5 PLL and Clock No. of Pins Signal Name Signal Type State During Reset 1 EXTAL Input Input 1 XTAL Input/ Output Chip-driven Signal Description External Crystal Oscillator Input—This input should be connected to an 8MHz external crystal or ceramic resonator. For more information, please refer to Section 3.5.
Table 2-7 Data Bus Signals No. of Pins Signal Name Signal Type State During Reset 16 D0–D15 Input/O utput Tri-stated Signal Description Data Bus— D0–D15 specify the data for external Program or Data memory accesses. D0–D15 are tri-stated when the external bus is inactive. Internal pull-ups may be active. Table 2-8 Bus Control Signals No. of Pins Signal Name Signal Type State During Reset 1 PS Output Tri-stated Program Memory Select—PS is asserted low for external Program memory access.
Pulse Width Modulator (PWM) Signals Table 2-9 Interrupt and Program Control Signals (Continued) No. of Pins Signal Name Signal Type State During Reset 1 RESET Input (Schmitt) Input Signal Description Reset—This input is a direct hardware reset on the processor. When RESET is asserted low, the controller is initialized and placed in the Reset state. A Schmitt trigger input is used for noise immunity. When the RESET pin is deasserted, the initial chip operating mode is latched from the EXTBOOT pin.
2.7 Serial Peripheral Interface (SPI) Signals Table 2-11 Serial Peripheral Interface (SPI) Signals No. of Pins Signal Name Signal Type State During Reset 1 MISO Input/Out put Input SPI Master In/Slave Out (MISO)—This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high impedance state if the slave device is not selected.
Quadrature Decoder Signals 2.8 Quadrature Decoder Signals Table 2-12 Quadrature Decoder (Quad Dec0) Signals No.
2.10 CAN Signals Table 2-14 CAN Module Signals No. of Pins Signal Name Signal Type State During Reset 1 MSCAN_ RX Input (Schmitt) Input 1 MSCAN_ TX Output Output Signal Description MSCAN Receive Data—This is the MSCAN input. This pin has an internal pull-up resistor. MSCAN Transmit Data—MSCAN output. CAN output is open-drain output and a pull-up resistor is needed. 2.11 Analog-to-Digital Converter (ADC) Signals Table 2-15 Analog to Digital Converter Signals No.
JTAG/OnCE 2.13 JTAG/OnCE Table 2-17 JTAG/On-Chip Emulation (OnCE) Signals No. of Pins Signal Name Signal Type State During Reset 1 TCK Input Input, pulled low Test Clock Input—This input pin provides a gated clock to synchronize the (Schmitt) internally test logic and shift serial data to the JTAG/OnCE port. The pin is connected internally to a pull-down resistor.
Absolute maximum ratings given in Table 3-1 are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to the device. The 56F803 DC/AC electrical specifications are preliminary and are from design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle.
General Characteristics Table 3-2 Recommended Operating Conditions Characteristic Symbol Min Typ Max Unit Voltage difference VSS to VSSA ΔVSS -0.1 - 0.1 V ADC reference voltage VREF 2.7 – VDDA V TA –40 – 85 °C Ambient operating temperature Table 3-3 Thermal Characteristics6 Value Characteristic Comments Symbol Unit Notes 100-pin LQFP Junction to ambient Natural convection Junction to ambient (@1m/sec) RθJA 41.7 °C/W 2 RθJMA 37.
4. Thermal Characterization Parameter, Psi-JT (ΨJT ), is the “resistance” from junction to reference point thermocouple on top center of case as defined in JESD51-2. ΨJT is a useful value to use to estimate junction temperature in steady state customer environments. 5.
DC Electrical Characteristic Table 3-4 DC Electrical Characteristics (Continued) Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz Characteristic Symbol Min Typ Max Unit Input current high (analog inputs, VIN=VDDA)2 IIHA -15 — 15 μA Input current low (analog inputs, VIN=VSSA)2 IILA -15 — 15 μA Output High Voltage (at IOH) VOH VDD – 0.7 — — V Output Low Voltage (at IOL) VOL — — 0.
8. This low-voltage interrupt monitors the VDDA external power supply. VDDA is generally connected to the same potential as VDD via separate traces. If VDDA drops below VEIO, an interrupt is generated. Functionality of the device is guaranteed under transient conditions when VDDA>VEIO (between the minimum specified VDD and the point when the VEIO interrupt is generated). 9. This low voltage interrupt monitors the internally regulated core power supply.
Flash Memory Characteristics Low VIH Input Signal High 90% 50% 10% Midpoint1 VIL Fall Time Rise Time Note: The midpoint is VIL + (VIH – VIL)/2.
5. Defines program cycle 6. Defines erase cycle 7. Defines mass erase cycle, erase whole block 8.
Flash Memory Characteristics Table 3-7 Flash Timing Parameters (Continued) Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF Characteristic Symbol Min Typ Max Unit Figure Cumulative program HV period2 Thv – 3 – ms Figure 3-4 Program hold time3 Tpgh – – – Figure 3-4 Address/data set up time3 Tads – – – Figure 3-4 Address/data hold time3 Tadh – – – Figure 3-4 1. One cycle is equal to an erase program and read. 2.
IFREN XADR XE YE=SE=OE=MAS1=0 ERASE Tnvs NVSTR Tnvh Trcv Terase Figure 3-5 Flash Erase Cycle IFREN XADR XE MAS1 YE=SE=OE=0 ERASE Tnvs NVSTR Tnvh1 Tme Trcv Figure 3-6 Flash Mass Erase Cycle 56F803 Technical Data, Rev.
External Clock Operation 3.5 External Clock Operation The 56F803 system clock can be derived from an external crystal or an external system clock signal. To generate a reference frequency using the internal oscillator, a reference crystal must be connected between the EXTAL and XTAL pins. 3.5.1 Crystal Oscillator The internal oscillator is also designed to interface with a parallel-resonant crystal resonator in the frequency range specified for the external crystal in Table 3-9.
3.5.2 Ceramic Resonator It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system design can tolerate the reduced signal integrity. In Figure 3-8, a typical ceramic resonator circuit is shown. Refer to supplier’s recommendations when selecting a ceramic resonator and associated components. The resonator and components should be mounted as close as possible to the EXTAL and XTAL pins.
External Clock Operation Table 3-8 External Clock Operation Timing Requirements3 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C Characteristic Symbol Min Typ Max Unit Frequency of operation (external clock driver)1 fosc 0 — 80 MHz Clock Pulse Width2, 3 tPW 6.25 — — ns 1. See Figure 3-9 for details on using the recommended connection of an external clock driver. 2. The high or low pulse width must be no smaller than 6.25ns or the chip will not function.
3.5.4 Phase Locked Loop Timing Table 3-9 PLL Timing Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C Characteristic Symbol Min Typ Max Unit fosc 4 8 10 MHz fout/2 40 — 110 MHz PLL stabilization time 3 0o to +85oC tplls — 1 10 ms PLL stabilization time3 -40o to 0oC tplls — 100 200 ms External reference crystal frequency for the PLL1 PLL output frequency 2 1.
External Bus Asynchronous Timing Table 3-10 External Bus Asynchronous Timing1, 2 (Continued) Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz Characteristic Symbol Min Max Unit Input Data Hold to RD Deasserted tDRD 0 — ns RD Assertion Width Wait states = 0 Wait states > 0 tRD 19 (T*WS) + 19 — — ns ns Address Valid to Input Data Valid Wait states = 0 Wait states > 0 tAD — — 1 (T*WS) + 1 ns ns -4.4 — ns — — 2.4 (T*WS) + 2.
1. Timing is both wait state and frequency dependent. In the formulas listed, WS = the number of wait states and T = Clock Period. For 80MHz operation, T = 12.5ns. 2. Parameters listed are guaranteed by design. To calculate the required access time for an external memory for any frequency < 80Mhz, use this formula: Top = Clock period @ desired operating frequency WS = Number of wait states Memory Access Time = (Top*WS) + (Top- 11.
Reset, Stop, Wait, Mode Select, and Interrupt Timing Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing (Continued)1, 5 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF Characteristic Symbol Min Max Unit See Figure Edge-sensitive Interrupt Request Width tIRW 1.
RESET tRA tRAZ tRDA A0–A15, D0–D15 First Fetch PS, DS, RD, WR First Fetch Figure 3-12 Asynchronous Reset Timing IRQA, IRQB tIRW Figure 3-13 External Interrupt Timing (Negative-Edge-Sensitive) 56F803 Technical Data, Rev.
Reset, Stop, Wait, Mode Select, and Interrupt Timing A0–A15, PS, DS, RD, WR First Interrupt Instruction Execution tIDM IRQA, IRQB a) First Interrupt Instruction Execution General Purpose I/O Pin tIG IRQA, IRQB b) General Purpose I/O Figure 3-14 External Level-Sensitive Interrupt Timing IRQA, IRQB tIRI A0–A15, PS, DS, RD, WR First Interrupt Vector Instruction Fetch Figure 3-15 Interrupt from Wait State Timing tIW IRQA tIF A0–A15, PS, DS, RD, WR First Instruction Fetch Not IRQA Interrupt Vector
tIRQ IRQA tII A0–A15 PS, DS, RD, WR First IRQA Interrupt Instruction Fetch Figure 3-17 Recovery from Stop State Using IRQA Interrupt Service 3.8 Serial Peripheral Interface (SPI) Timing Table 3-12 SPI Timing1 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz Characteristic Symbol Cycle time Master Slave Min Max Unit 50 25 — — ns ns — 25 — — ns ns — 100 — — ns ns 17.6 12.5 — — 24.
Serial Peripheral Interface (SPI) Timing Table 3-12 SPI Timing1 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz Characteristic Symbol Data Valid for outputs Master Slave (after enable edge) tDV Data invalid Master Slave tDI Rise time Master Slave tR Fall time Master Slave tF Min Max Unit — — 4.5 20.4 ns ns 0 0 — — ns ns — — 11.5 10.0 ns ns — — 9.7 9.
SS (Input) SS is held High on master tC tF tR tCL SCLK (CPOL = 0) (Output) tCH tF tCL SCLK (CPOL = 1) (Output) tCH tDS tDH tR MISO (Input) MSB in tDI tDV(ref) MOSI (Output) Bits 14–1 Master MSB out LSB in tDV Bits 14– 1 tF Master LSB out tR Figure 3-19 SPI Master Timing (CPHA = 1) 56F803 Technical Data, Rev.
Serial Peripheral Interface (SPI) Timing SS (Input) tC tF tCL SCLK (CPOL = 0) (Input) tELG tR tCH tELD tCL SCLK (CPOL = 1) (Input) tCH tA MISO (Output) Slave MSB out Bits 14–1 tDS tDV tDH MOSI (Input) MSB in tF tR Bits 14–1 tD Slave LSB out tDI tDI LSB in Figure 3-20 SPI Slave Timing (CPHA = 0) 56F803 Technical Data, Rev.
SS (Input) tC tF tR tCL SCLK (CPOL = 0) (Input) tCH tELD SCLK (CPOL = 1) (Input) tDV tELG tCL tCH tR tD tF tA MISO (Output) Slave MSB out Bits 14–1 Slave LSB out tDV tDS tDI tDH MOSI (Input) MSB in Bits 14–1 LSB in Figure 3-21 SPI Slave Timing (CPHA = 1) 3.9 Quad Timer Timing Table 3-13 Timer Timing1, 2 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.
Quadrature Decoder Timing Table 3-13 Timer Timing1, 2 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz Timer output high/low period 1. POUTHL 1T — ns In the formulas listed, T = clock cycle. For 80MHz operation, T = 12.5ns. 2. Parameters listed are guaranteed by design. Timer Inputs PIN PINHL PINHL Timer Outputs POUT POUTHL POUTHL Figure 3-22 Timer Timing 3.
PPH PPH PPH PPH Phase A (Input) PIN PHL PHL Phase B (Input) PIN PHL PHL Figure 3-23 Quadrature Decoder Timing 3.11 Serial Communication Interface (SCI) Timing Table 3-15 SCI Timing4 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz Characteristic Symbol Min Max Unit BR — (fMAX*2.5)/(80) Mbps RXD2 Pulse Width RXDPW 0.965/BR 1.04/BR ns TXD3 Pulse Width TXDPW 0.965/BR 1.04/BR ns Baud Rate1 1.
Analog-to-Digital Converter (ADC) Characteristics TXD SCI receive data pin (Input) TXDPW Figure 3-25 TXD Pulse Width 3.12 Analog-to-Digital Converter (ADC) Characteristics Table 3-16 ADC Characteristics Characteristic Symbol Min Typ Max Unit VADCIN 01 — VREF2 V Resolution RES 12 — 12 Bits Integral Non-Linearity3 INL — +/- 2.5 +/- 4 LSB4 Differential Non-Linearity DNL — +/- 0.9 +/- 1 LSB4 ADC input voltages Monotonicity GUARANTEED ADC internal clock5 fADIC 0.
Table 3-16 ADC Characteristics Characteristic Symbol Min Typ Max Unit ADC Quiescent Current (both ADCs) IADC — 50 — mA VREF Quiescent Current (both ADCs) IVREF — 12 16.5 mA 1. For optimum ADC performance, keep the minimum VADCIN value > 25mV. Inputs less than 25mV may convert to a digital output code of 0. 2. VREF must be equal to or less than VDDA and must be greater than 2.7V. For optimal ADC performance, set VREF to VDDA-0.3V. 3. Measured in 10-90% range. 4. LSB = Least Significant Bit.
Controller Area Network (CAN) Timing 1. If Wakeup glitch filter is enabled during the design initialization and also CAN is put into SLEEP mode then, any bus event (on MSCAN_RX pin) whose duration is less than 5 micro seconds is filtered away. However, a valid CAN bus wakeup detection takes place for a wakeup pulse equal to or greater than 5 microseconds. The value of 5 microseconds originates from the fact that the CAN wakeup message consists of 5 dominant bits at the highest possible baud rate of 1Mbps.
3.14 JTAG Timing Table 3-18 JTAG Timing1, 3 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz Characteristic Symbol Min Max Unit TCK frequency of operation2 fOP DC 10 MHz TCK cycle time tCY 100 — ns TCK clock pulse width tPW 50 — ns TMS, TDI data set-up time tDS 0.4 — ns TMS, TDI data hold time tDH 1.2 — ns TCK low to TDO data valid tDV — 26.6 ns TCK low to TDO tri-state tTS — 23.
JTAG Timing TCK (Input) tDS TDI TMS (Input) tDH Input Data Valid tDV TDO (Output) Output Data Valid tTS TDO (Output) tDV TDO (Output) Output Data Valid Figure 3-29 Test Access Port Timing Diagram TRST (Input) tTRST Figure 3-30 TRST Timing Diagram DE tDE Figure 3-31 OnCE—Debug Event 56F803 Technical Data, Rev.
Part 4 Packaging 4.1 Package and Pin-Out Information 56F803 D9 D8 D7 D6 D5 D4 D3 VSS VDD D2 D1 D0 VCAPC SCLK MOSI MISO SS TD2 TD1 CLKO DE RESET EXTBOOT RXD0 TXD0 This section contains package and pin-out information for the 100-pin LQFP configuration of the 56F803.
Package and Pin-Out Information 56F803 Table 4-1 56F803 Pin Identification By Pin Number Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
S 0.15 (0.006) S AC T-U Z S S -T- B 0.15 0.15 (0.006) S AC Z -Z- (0.006) S V AC Z S S T-U T-U S S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6.
Thermal Design Considerations Please see www.freescale.com for the most current case outline. Part 5 Design Considerations 5.
How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.
