56F826 Data Sheet Preliminary Technical Data 56F800 16-bit Digital Signal Controllers DSP56F826 Rev. 14 01/2007 freescale.
56F826 General Description • Up to 40 MIPS at 80MHz core frequency • One Serial Port Interface (SPI) • DSP and MCU functionality in a unified, C-efficient architecture • One additional SPI or two optional Serial Communication Interfaces (SCI) • Hardware DO and REP loops • One Synchronous Serial Interface (SSI) • MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes • One General Purpose Quad Timer • JTAG/OnCE™ for debugging
Part 1 Overview 1.1 56F826 Features 1.1.1 • • • • • • • • • • • • • • 1.1.
6F826 Description • • • • • • • • • 1.1.
This controller also provides a full set of standard programmable peripherals including one Synchronous Serial Interface (SSI), one Serial Peripheral Interface (SPI), the option to select a second SPI or two Serial Communications Interfaces (SCIs), and one Quad Timer. The SSI, SPI, and Quad Timer can be used as General Purpose Input/Outputs (GPIOs) if a timer function is not required. 1.
Data Sheet Conventions 1.5 Data Sheet Conventions This data sheet uses the following conventions: OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is active when low. “asserted” A high true (active high) signal is high or a low true (active low) signal is low. “deasserted” A high true (active high) signal is low or a low true (active low) signal is high.
Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F826 are organized into functional groups, as shown in Table 2-1 and as illustrated in Figure 2-1. Table 2-1 describes the signal or signals present on a pin.
Introduction 2.5V Power VDD 3 8 GPIOB0–7 3.3V Analog Power VDDA 1 8 GPIOD0–7 3.
2.2 Signals and Package Information All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always enabled. Exceptions: 1. When a pin is owned by GPIO, then the pull-up may be disabled under software control. 2. TCK has a weak pull-down circuit always active. Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP Signal Name Pin No.
Signals and Package Information Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued) Signal Name Pin No. Type XTAL 62 Output (CLOCKIN) Input Description Crystal Oscillator Output—This output connects the internal crystal oscillator output to an external crystal or ceramic resonator. If an external clock source over 4MHz is used, XTAL must be used as the input and EXTAL connected to VSS. For more information, please refer to Section 3.6.3.
Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued) Signal Name Pin No. Type A8 (GPIOA0) 14 Output A9 (GPIOA1) 13 A10 (GPIOA2) 12 A11 (GPIOA3) 11 A12 (GPIOA4) 10 A13 (GPIOA5) 9 A14 (GPIOA6) 8 A15 (GPIOA7) 7 D0 34 D1 35 D2 36 D3 37 D4 38 D5 39 D6 40 D7 41 D8 42 D9 43 D10 44 D11 46 D12 47 D13 48 D14 49 D15 50 PS 29 Output Program Memory Select—PS is asserted low for external program memory access.
Signals and Package Information Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued) Signal Name Pin No. Type Description RD 26 Output Read Enable—RD is asserted during external memory read cycles. When RD is asserted low, pins D0–D15 become inputs and an external device is enabled onto the device data bus. When RD is deasserted high, the external data is latched inside the device. When RD is asserted, it qualifies the A0–A15, PS, and DS pins.
Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued) Signal Name Pin No. Type Description GPIOB0 66 GPIOB1 67 Input or Output Port B GPIO—These eight dedicated General Purpose I/O (GPIO) pins can be individually programmed as input or output pins.
Signals and Package Information Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued) Signal Name Pin No. Type Description SRCK 53 Input/Output SSI Serial Receive Clock (SRCK)—This bidirectional pin provides the serial bit rate clock for the Receive section of the SSI. The clock signal can be continuous or gated and can be used by both the transmitter and receiver in synchronous mode.
Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued) Signal Name Pin No. Type MISO 86 Input/Output SPI Master In/Slave Out (MISO)—This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected. Input/Output Port F GPIO—This General Purpose I/O (GPIO) pin can be individually programmed as input or output.
Signals and Package Information Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued) Signal Name Pin No. Type IRQA 32 Input (Schmitt) Description External Interrupt Request A—The IRQA input is a synchronized external interrupt request that indicates that an external device is requesting service. It can be programmed to be level-sensitive or negative-edge-triggered. If level-sensitive triggering is selected, an external pull-up resistor is required for wired-OR operation.
Part 3 Specifications 3.1 General Characteristics The 56F826 is fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term “5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V- and 5V-compatible I/O voltage levels. A standard 3.
General Characteristics Table 3-1 Absolute Maximum Ratings Characteristic Supply voltage, core Supply voltage, IO Supply voltage, Analog Symbol Min Max Unit VDD1 VSS – 0.3 VSS + 3.0 V VDDIO2 VSSIO – 0.3 VSSA – 0.3 VSSIO + 4.0 VSSA + 4.0 V VDDA 2 Analog input voltages - XTAL, EXTAL VIN VINA VSSIO – 0.3 VSSA – 0.3 VSSIO + 5.5 VDDA + 0.3 V Voltage difference VDD to VDD_IO, VDDA ΔVDD - 0.3 0.3 V Voltage difference VSS to VSS _IO, VSSA ΔVSS - 0.3 0.
Table 3-3 Thermal Characteristics6 Value Characteristic Comments Symbol Unit Notes 100-pin LQFP Junction to ambient Natural convection Junction to ambient (@1m/sec) RθJA 48.3 °C/W 2 RθJMA 43.9 °C/W 2 Junction to ambient Natural convection Four layer board (2s2p) RθJMA (2s2p) 40.7 °C/W 1.2 Junction to ambient (@1m/sec) Four layer board (2s2p) RθJMA 38.6 °C/W 1,2 Junction to case RθJC 13.5 °C/W 3 Junction to center of case ΨJT 1.
DC Electrical Characteristics 3.2 DC Electrical Characteristics Table 3-4 DC Electrical Characteristics Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz Characteristic Symbol Min Typ Max Unit Input high voltage (XTAL/EXTAL) VIHC 2.25 — 3.6 V Input low voltage (XTAL/EXTAL) VILC 0 — 0.5 V Input high voltage (Schmitt trigger inputs)1 VIHS 2.2 — 5.5 V Input low voltage (Schmitt trigger inputs)1 VILS -0.
Table 3-4 DC Electrical Characteristics (Continued) Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz Characteristic Symbol Min Typ Max Unit CIN — 8 — pF Output capacitance COUT — 12 — pF VDD supply current IDDT5 Run 6 — 47 75 mA Wait7 — 21 36 mA Stop — 2 8 mA Input capacitance Low Voltage Interrupt, VDDIO power supply8 VEIO 2.4 2.7 3.0 V Low Voltage Interrupt, VDD power supply9 VEIC 2.
Supply Voltage Sequencing and Separation Cautions 100 75 IDD (mA) IDD Digital IDD Analog IDD Total 50 25 0 20 40 60 80 Freq. (MHz) Figure 3-1 Maximum Run IDD vs. Frequency (see Note 6. in Table 3-4) 3.3 Supply Voltage Sequencing and Separation Cautions DC Power Supply Voltage Figure 3-2 shows two situations to avoid in sequencing the VDD and VDDIO, VDDA supplies. 3.3V VDDIO, VDDA 2 2.5V Supplies Stable VDD 1 0 Time Notes: 1. VDD rising before VDDIO, VDDA 2.
VDD should not be allowed to rise early (1). This is usually avoided by running the regulator for the VDD supply (2.5V) from the voltage generated by the 3.3V VDDIO supply, see Figure 3-3. This keeps VDD from rising faster than VDDIO. VDD should not rise so late that a large voltage difference is allowed between the two supplies (2). Typically this situation is avoided by using external discrete diodes in series between supplies, as shown in Figure 3-3.
Flash Memory Characteristics Data2 Valid Data1 Valid Data1 Data3 Valid Data2 Data3 Data Tri-stated Data Invalid State Data Active Data Active Figure 3-5 Signal States 3.5 Flash Memory Characteristics Table 3-5 Flash Memory Truth Table Mode XE1 YE2 SE3 OE4 PROG5 ERASE6 MAS17 NVSTR8 Standby L L L L L L L L Read H H H H L L L L Word Program H H L L H L L H Page Erase H L L L L H L H Mass Erase H L L L L H H H 1.
Table 3-7 Flash Timing Parameters Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.
Flash Memory Characteristics IFREN XADR XE Tadh YADR YE DIN Tads PROG Tnvs Tprog Tpgh NVSTR Tpgs Tnvh Thv Trcv Figure 3-6 Flash Program Cycle IFREN XADR XE YE=SE=OE=MAS1=0 ERASE Tnvs NVSTR Tnvh Terase Trcv Figure 3-7 Flash Erase Cycle 56F826 Technical Data, Rev.
IFREN XADR XE MAS1 YE=SE=OE=0 ERASE Tnvs NVSTR Tnvh1 Tme Trcv Figure 3-8 Flash Mass Erase Cycle 3.6 External Clock Operation The 56F826 system clock can be derived from a crystal or an external system clock signal. To generate a reference frequency using the internal oscillator, a reference crystal must be connected between the EXTAL and XTAL pins. 3.6.
External Clock Operation as a typical circuit board trace capacitance the parallel load capacitance presented to the crystal is 9pF as determined by the following equation: CL = CL1 * CL2 CL1 + CL2 + Cs = 12 * 12 12 + 12 + 3 = 6 + 3 = 9pF This is the value load capacitance that should be used when selecting a crystal and determining the actual frequency of operation of the crystal oscillator circuit.
3.6.3 External Clock Source The recommended method of connecting an external clock is given in Figure 3-11. The external clock source is connected to XTAL and the EXTAL pin is held VDDA/2. 56F826 XTAL EXTAL External Clock VDDA/2 Figure 3-11 Connecting an External Clock Signal Table 3-8 External Clock Operation Timing Requirements Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.
External Bus Asynchronous Timing 3.6.4 Phase Locked Loop Timing Table 3-9 PLL Timing Operating Conditions: VSSIO = VSS = VSSA = 0V, VDDA = VDDIO = 3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL < 50pF, fop = 80MHz Characteristic External reference crystal frequency for the PLL1 PLL output frequency2 PLL stabilization time 3 -40o to +85oC Symbol Min Typ Max Unit fosc 2 4 6 MHz fout/2 40 — 110 MHz tplls — 1 10 ms 1.
Table 3-10 External Bus Asynchronous Timing1, 2 (Continued) Operating Conditions: VSSIO = VSS = VSSA = 0V, VDDA = VDDIO = 3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz Characteristic Symbol Min Max Unit Input Data Hold to RD Deasserted tDRD 0 — ns RD Assertion Width Wait states = 0 Wait states > 0 tRD 19 (T*WS) + 19 — — ns ns Address Valid to Input Data Valid Wait states = 0 Wait states > 0 tAD — — 1 (T*WS) + 1 ns ns -4.4 — ns — — 2.4 (T*WS) + 2.
External Bus Asynchronous Timing A0–A15, PS, DS (See Note) tARDD tRDA tARDA RD tAWR tWRWR tWR tWRRD tRDWR WR tAD tWRD tDOS D0–D15 tRDRD tRD tRDD tDRD tDOH Data Out Data In Note: During read-modify-write instructions and internal instructions, the address lines do not change state. Figure 3-13 External Bus Asynchronous Timing 56F826 Technical Data, Rev.
3.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 5 Operating Conditions: VSSIO = VSS = VSSA = 0V, VDDA = VDDIO = 3.0–3.6V, VDD = 2.25–2.
Reset, Stop, Wait, Mode Select, and Interrupt Timing RESET tRA tRAZ tRDA A0–A15, D0–D15 First Fetch PS, DS, RD, WR First Fetch Figure 3-14 Asynchronous Reset Timing IRQA, IRQB tIRW Figure 3-15 External Interrupt Timing (Negative-Edge-Sensitive) A0–A15, PS, DS, RD, WR First Interrupt Instruction Execution tIDM IRQA, IRQB a) First Interrupt Instruction Execution General Purpose I/O Pin tIG IRQA, IRQB b) General Purpose I/O Figure 3-16 External Level-Sensitive Interrupt Timing 56F826 Technical
IRQA, IRQB tIRI A0–A15, PS, DS, RD, WR First Interrupt Vector Instruction Fetch Figure 3-17 Interrupt from Wait State Timing tIW IRQA tIF A0–A15, PS, DS, RD, WR First Instruction Fetch Not IRQA Interrupt Vector Figure 3-18 Recovery from Stop State Using Asynchronous Interrupt Timing tIRQ IRQA tII A0–A15 PS, DS, RD, WR First IRQA Interrupt Instruction Fetch Figure 3-19 Recovery from Stop State Using IRQA Interrupt Service 56F826 Technical Data, Rev.
Serial Peripheral Interface (SPI) Timing 3.9 Serial Peripheral Interface (SPI) Timing Table 3-12 SPI Timing1 Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.
SS SS is held High on master (Input) tC tR tF tCL SCLK (CPOL = 0) (Output) tCH tF tR tCL SCLK (CPOL = 1) (Output) tDH tCH tDS MISO (Input) MSB in Bits 14–1 LSB in tDI MOSI (Output) tDV Master MSB out Bits 14–1 tDI(ref) Master LSB out tR tF Figure 3-20 SPI Master Timing (CPHA = 0) SS (Input) SS is held High on master tC tF tCL SCLK (CPOL = 0) (Output) tCH tR tF tCL SCLK (CPOL = 1) (Output) tCH tDS tDH tR MISO (Input) MSB in tDI tDV(ref) MOSI (Output) Bits 14–1 Mas
Serial Peripheral Interface (SPI) Timing SS (Input) tC tF tCL SCLK (CPOL = 0) (Input) tELG tR tCH tELD tCL SCLK (CPOL = 1) (Input) tCH tA MISO (Output) Slave MSB out tF tR Bits 14–1 tDS Slave LSB out tDV MSB in tDI tDI tDH MOSI (Input) tD Bits 14–1 LSB in Figure 3-22 SPI Slave Timing (CPHA = 0) SS (Input) tC tF tR tCL SCLK (CPOL = 0) (Input) tCH tELD SCLK (CPOL = 1) (Input) tDV tELG tCL tCH tR MISO (Output) Slave MSB out Bits 14–1 tDV tDS tDH MOSI (Input) tD t
3.10 Synchronous Serial Interface (SSI) Timing Table 3-13 SSI Master Mode1 Switching Characteristics Operating Conditions: VSSIO = VSS = VSSA = 0V, VDDA = VDDIO = 3.0–3.6V, VDD = 2.25–2.
Synchronous Serial Interface (SSI) Timing 3. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR) and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS in the tables and in the figures. 4. 50% duty cycle 5.
Table 3-14 SSI Slave Mode1 Switching Characteristics Operating Conditions: VSSIO = VSS = VSSA = 0V, VDDA = VDDIO = 3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz Parameter Symbol Min Typ Max Units — 102 MHz STCK frequency fs STCK period3 tSCKW 100 — — ns STCK high time tSCKH 504 — — ns STCK low time tSCKL 504 — — ns — TBD — ns 0.
Synchronous Serial Interface (SSI) Timing Table 3-14 SSI Slave Mode1 Switching Characteristics Operating Conditions: VSSIO = VSS = VSSA = 0V, VDDA = VDDIO = 3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz Parameter Symbol Min Typ Max Units Synchronous Operation (in addition to standard external clock parameters) SRXD Setup time before STCK low - Slave tTSS 4 — — SRXD Hold time after STCK low - Slave tTHS 4 — — 1.
tSCKW tSCKH tSCKL STCK input tTFSBLS tTFSBHS STFS (bl) input tTFSWHS tTFSWLS STFS (wl) input tFTXES tFTXVS tTXNVS tTXVS tTXES tTXHIS First Bit STXD SRCK input Last Bit tRFBLS tRFSBHS SRFS (bl) input tRFSWHS tRFSWLS SRFS (wl) input tSS tTSS tHS tTHS SRXD Figure 3-25 Slave Mode Clock Timing 3.11 Quad Timer Timing Table 3-15 Timer Timing1, 2 Operating Conditions: VSSIO = VSS = VSSA = 0V, VDDA = VDDIO = 3.0–3.6V, VDD = 2.25–2.
Serial Communication Interface (SCI) Timing Timer Inputs PIN PINHL PINHL Timer Outputs POUT POUTHL POUTHL Figure 3-26 Quad Timer Timing 3.12 Serial Communication Interface (SCI) Timing Table 3-16 SCI Timing4 Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz Characteristic Symbol Min Max Unit BR — (fMAX*2.5)/(80) Mbps RXD2 Pulse Width RXDPW 0.965/BR 1.04/BR ns TXD3 Pulse Width TXDPW 0.965/BR 1.
TXD SCI receive data pin (Input) TXDPW Figure 3-28 TXD Pulse Width 3.13 JTAG Timing Table 3-17 JTAG Timing1, 3 Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz Characteristic Symbol Min Max Unit TCK frequency of operation2 fOP DC 10 MHz TCK cycle time tCY 100 — ns TCK clock pulse width tPW 50 — ns TMS, TDI data set-up time tDS 0.4 — ns TMS, TDI data hold time tDH 1.
JTAG Timing TCK (Input) tDS TDI TMS (Input) tDH Input Data Valid tDV TDO (Output) Output Data Valid tTS TDO (Output) tDV TDO (Output) Output Data Valid Figure 3-30 Test Access Port Timing Diagram TRST (Input) tTRST Figure 3-31 TRST Timing Diagram DE tDE Figure 3-32 OnCE—Debug Event 56F826 Technical Data, Rev.
Part 4 Packaging 4.1 Package and Pin-Out Information 56F826 TCK TCS DE TXD0 RXD0 VSS VDD TXD1 RXD1 TA0 TA1 TA2 TA3 SS MISO MOSI SCLK GPIOD7 GPIOD6 VSSIO VDDIO GPIOD5 GPIOD4 GPIOD3 GPIOD2 This section contains package and pin-out information for the 100-pin LQFP configuration of the 56F826.
Package and Pin-Out Information 56F826 Table 4-1 56F826 Pin Identification by Pin Number Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No.
S 0.15(0.006) AC T-U S Z S S -T- 0.15(0.006) 0.15(0.006) S AC Z B -Z- S V AC Z S S T-U T-U S S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6.
Thermal Design Considerations Part 5 Design Considerations 5.
• Use the value obtained by the equation (TJ – TT)/PD, where TT is the temperature of the package case determined by a thermocouple. The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from the junction.
Electrical Design Considerations • • Because the controller’s output signals have fast rise and fall times, PCB trace lengths should be minimal. Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and VSS circuits. • Take special care to minimize noise levels on the VREF, VDDA and VSSA pins.
Part 6 Ordering Information Table 6-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor sales office or authorized distributor to determine availability and to order parts. Table 6-1 56F826 Ordering Information Part Supply Voltage Package Type Pin Count Ambient Frequency (MHz) Order Number 56F826 3.0–3.6 V 2.25-2.75 V Plastic Quad Flat Pack (LQFP) 100 80 DSP56F826BU80 56F826 3.0–3.6 V 2.25-2.
Electrical Design Considerations 56F826 Technical Data, Rev.
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