Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Transducer Converter, Bidirectional SO 8

1. General description

The Gunning Transceiver Logic - Transceiver Voltage Clamps (GTL-TVC) provide

high-speed voltage translation with low ON-state resistance and minimal propagation

delay. The GTL2002 provides 2 NMOS pass transistors (Sn and Dn) with a common gate

(GREF) and a reference transistor (SREF and DREF). The device allows bidirectional

voltage translations between 1.0 V and 5.0 V without use of a direction pin.

When the Sn or Dn port is LOW the clamp is in the ON-state and a low resistance

connection exists between the Sn and Dn ports. Assuming the higher voltage is on the Dn

port, when the Dn port is HIGH, the voltage on the Sn port is limited to the voltage set by

the reference transistor (SREF). When the Sn port is HIGH, the Dn port is pulled to V

the pull-up resistors. This functionality allows a seamless translation between higher and

lower voltages selected by the user, without the need for directional control.

All transistors have the same electrical characteristics and there is minimal deviation from

one output to another in voltage or propagation delay. This is a benefit over discrete

transistor voltage translation solutions, since the fabrication of the transistors is

symmetrical. Because all transistors in the device are identical, SREF and DREF can be

located on any of the other two matched Sn/Dn transistors, allowing for easier board

layout. The translator's transistors provide excellent ESD protection to lower voltage

devices and at the same time protect less ESD-resistant devices.

2. Features and benefits

 2-bit bidirectional low voltage translator

 Allows voltage level translation between 1.0V, 1.2V, 1.5V, 1.8V, 2.5V, 3.3V and 5V

buses, which allows direct interface with GTL, GTL+, LVTTL/TTL and 5 V CMOS

levels

 Provides bidirectional voltage translation with no direction pin

 Low 6.5  ON-state resistance (R

) between input and output pins (Sn/Dn)

 Supports hot insertion

 No power supply required; will not latch up

 5 V tolerant inputs

 Low standby current

 Flow-through pinout for ease of printed-circuit board trace routing

 ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per

JESD22-C101

 Packages offered: SO8, TSSOP8 (MSOP8), VSSOP8, XQFN8

GTL2002

2-bit bidirectional low voltage translator

Rev. 8 — 19 August 2013 Product data sheet

Summary of content (27 pages)

PAGE 1
GTL2002 2-bit bidirectional low voltage translator Rev. 8 — 19 August 2013 Product data sheet 1. General description The Gunning Transceiver Logic - Transceiver Voltage Clamps (GTL-TVC) provide high-speed voltage translation with low ON-state resistance and minimal propagation delay. The GTL2002 provides 2 NMOS pass transistors (Sn and Dn) with a common gate (GREF) and a reference transistor (SREF and DREF). The device allows bidirectional voltage translations between 1.0 V and 5.
PAGE 2
GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator 3. Applications  Any application that requires bidirectional or unidirectional voltage level translation from any voltage between 1.0 V and 5.0 V to any voltage between 1.0 V and 5.0 V  The open-drain construction with no direction pin is ideal for bidirectional low voltage (e.g., 1.0 V, 1.2 V, 1.5 V, or 1.8 V) processor I2C-bus port translation to the normal 3.3 V or 5.
PAGE 3
GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator 5. Functional diagram DREF GREF SREF D1 D2 S1 S2 002aac784 Fig 1. Functional diagram 6. Pinning information 6.1 Pinning GND 1 8 GREF SREF 2 7 DREF S1 3 6 D1 D2 GTL2002D 5 1 SREF 2 S1 3 S2 4 GTL2002DP Pin configuration for SO8 Fig 3.
PAGE 4
GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator 6.2 Pin description Table 3. Symbol Pin description Pin Description SO8, TSSOP8, VSSOP8 XQFN8U GND 1 4 ground (0 V) SREF 2 1 source of reference transistor S1 3 2 port S1 S2 4 3 port S2 D2 5 5 port D2 D1 6 6 port D1 DREF 7 7 drain of reference transistor GREF 8 8 gate of reference transistor 7. Functional description Refer to Figure 1 “Functional diagram”. 7.1 Function selection Table 4.
PAGE 5
GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator 8. Application design-in information 8.1 Bidirectional translation For the bidirectional clamping configuration, higher voltage to lower voltage or lower voltage to higher voltage, the GREF input must be connected to DREF and both pins pulled to HIGH side VCC through a pull-up resistor (typically 200 k). A filter capacitor on DREF is recommended.
PAGE 6
GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator 8.2 Unidirectional down translation For unidirectional clamping, higher voltage to lower voltage, the GREF input must be connected to DREF and both pins pulled to the higher side VCC through a pull-up resistor (typically 200 k). A filter capacitor on DREF is recommended. Pull-up resistors are required if the chip set I/O are open-drain.
PAGE 7
GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator 8.4 Sizing pull-up resistor The pull-up resistor value needs to limit the current through the pass transistor when it is in the ON state to about 15 mA. This will guarantee a pass voltage of 260 mV to 350 mV. If the current through the pass transistor is higher than 15 mA, the pass voltage will also be higher in the ON state.
PAGE 8
GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator 9. Limiting values Table 7. Limiting values[1] In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Min Max Unit voltage on pin SREF [2] 0.5 +7.0 V VDREF voltage on pin DREF [2] 0.5 +7.0 V VGREF voltage on pin GREF [2] 0.5 +7.0 V voltage on port Sn [2] 0.5 +7.0 V VDn voltage on port Dn [2] 0.5 +7.
PAGE 9
GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator 11. Static characteristics Table 9. Static characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit VOL LOW-level output voltage VDD = 3.0 V; VSREF = 1.365 V; VSn or VDn = 0.175 V; Iclamp = 15.2 mA - 260 350 mV VIK input clamping voltage II = 18 mA; VGREF = 0 V - - 1.
PAGE 10
GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator 12. Dynamic characteristics 12.1 Dynamic characteristics for translator-type application Table 10. Dynamic characteristics for translator-type application Tamb = 40 C to +85 C; Vref = 1.365 V to 1.635 V; VDD1 = 3.0 V to 3.6 V; VDD2 = 2.36 V to 2.64 V; GND = 0 V; tr = tf  3.0 ns. Refer to Figure 11.
PAGE 11
GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator 12.2 Dynamic characteristics for CBT-type application Table 11. Dynamic characteristics for CBT-type application Tamb = 40 C to +85 C; VGREF = 5 V  0.5 V; GND = 0 V; tr = tf  3.0 ns; CL = 50 pF. Symbol tPD [1] Parameter Conditions [1] propagation delay Min Typ Max Unit - - 250 ps This parameter is warranted by the ON-state resistance at GREF = 4.5 V, but is not directly production tested.
PAGE 12
GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator 13. Test information VDD1 VDD2 200 kΩ DREF VDD2 150 kΩ GREF VDD2 150 kΩ 150 kΩ D2 D1 DUT SREF S2 S1 test jig Vref pulse generator 002aac790 Fig 11. Load circuit for translator-type applications RL from output under test 500 Ω CL 50 pF S1 7V open GND RL 500 Ω 002aab667 Test data are given in Table 12. CL = load capacitance; includes jig and probe capacitance. RL = load resistance. Fig 12.
PAGE 13
GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator 14.
PAGE 14
GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator 76623 SODVWLF WKLQ VKULQN VPDOO RXWOLQH SDFNDJH OHDGV ERG\ ZLGWK PP ' ( 627 $ ; F \ +( Y 0 $ = $ SLQ LQGH[ $ $ $ ș /S / GHWDLO ; H Z 0 ES PP VFDOH ',0(16,216 PP DUH WKH RULJLQDO GLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S Y Z \ = ș PP
PAGE 15
GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator 96623 SODVWLF YHU\ WKLQ VKULQN VPDOO RXWOLQH SDFNDJH OHDGV ERG\ ZLGWK PP ' ( 627 $ ; F \ +( Y 0 $ = 4 $ $ $ SLQ LQGH[ $ ș /S H / GHWDLO ; Z 0 ES PP VFDOH ',0(16,216 PP DUH WKH RULJLQDO GLPHQVLRQV 81,7 $ PD[ $ $ $ ES F PP ' ( H +( / /S 4 Y Z \ = ș
PAGE 16
GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator ;4)1 SODVWLF H[WUHPHO\ WKLQ TXDG IODW SDFNDJH QR OHDGV WHUPLQDOV ERG\ [ [ PP 627 ; ' % $ WHUPLQDO LQGH[ DUHD ( $ $ GHWDLO ; H Y Z E & & $ % & \ & \ H WHUPLQDO LQGH[ DUHD / PHWDO DUHD QRW IRU VROGHULQJ / 'LPHQVLRQV 8QLW PP PD[ QRP PLQ PP VFDOH $ $ E ' ( H H / Y /
PAGE 17
GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator 15. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 15.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits.
PAGE 18
GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator 15.
PAGE 19
GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 17. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 16.
PAGE 20
GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator î HQODUJHG VROGHU ODQG î î î ERDUG GLUHFWLRQ VROGHU ODQGV RFFXSLHG DUHD VROGHU UHVLVW SODFHPHQW DFFXUUDF\ 'LPHQVLRQV LQ PP VRW BIZ Fig 19. PCB footprint for SOT96-1 (SO8); wave soldering VROGHU ODQGV RFFXSLHG DUHD 'LPHQVLRQV LQ PP VRW BIU Fig 20.
PAGE 21
GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator )RRWSULQW LQIRUPDWLRQ IRU UHIORZ VROGHULQJ RI 96623 SDFNDJH 627 +[ *[ 3 +\ ' *\ %\ $\ & 3 ' [ *HQHULF IRRWSULQW SDWWHUQ 5HIHU WR WKH SDFNDJH RXWOLQH GUDZLQJ IRU DFWXDO OD\RXW VROGHU ODQG RFFXSLHG DUHD ',0(16,216 LQ PP 3 3 $\ %\ & ' ' *[ *\ +[ +\ VRW BIU Fig 21.
PAGE 22
GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator )RRWSULQW LQIRUPDWLRQ IRU UHIORZ VROGHULQJ RI ;4)1 SDFNDJH 627 +[ ' î & î +\ $\ 6/\ 6/[ VROGHU ODQG VROGHU SDVWH GHSRVLW VROGHU ODQG SOXV VROGHU SDVWH RFFXSLHG DUHD ',0(16,216 LQ PP $\ & ,VVXH GDWH ' 6/[ 6/\ +[ +\ VRW BIU Fig 22.
PAGE 23
GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator 17. Abbreviations Table 15.
PAGE 24
GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator 18. Revision history Table 16. Revision history Document ID Release date Data sheet status Change notice Supersedes GTL2002 v.8 20130819 Product data sheet - GTL2002 v.
PAGE 25
GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator 19. Legal information 19.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
PAGE 26
GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
PAGE 27
GTL2002 NXP Semiconductors 2-bit bidirectional low voltage translator 21. Contents 1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 8 8.1 8.2 8.3 8.4 9 10 11 12 12.1 12.2 13 14 15 15.1 15.2 15.3 15.4 16 17 18 19 19.1 19.2 19.3 19.4 20 21 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . .