Datasheet
GTL2002 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 8 — 19 August 2013 4 of 27
NXP Semiconductors
GTL2002
2-bit bidirectional low voltage translator
6.2 Pin description
7. Functional description
Refer to Figure 1 “Functional diagram”.
7.1 Function selection
[1] GREF should be at least 1.5 V higher than SREF for best translator operation.
[2] Sn is not pulled up or pulled down.
[3] Sn follows the Dn input LOW.
[4] V
TT
is equal to the SREF voltage.
[1] GREF should be at least 1.5 V higher than SREF for best translator operation.
[2] Dn is pulled up to V
CC
through an external resistor.
[3] Dn follows the Sn input LOW.
[4] V
TT
is equal to the SREF voltage.
Table 3. Pin description
Symbol Pin Description
SO8, TSSOP8,
XQFN8U
VSSOP8
GND 1 4 ground (0 V)
SREF 2 1 source of reference transistor
S1 3 2 port S1
S2 4 3 port S2
D2 5 5 port D2
D1 6 6 port D1
DREF 7 7 drain of reference transistor
GREF 8 8 gate of reference transistor
Table 4. Function selection, HIGH to LOW translation
Assuming Dn is at the higher voltage level.
H = HIGH voltage level; L = LOW voltage level; X = Don’t care.
GREF
[1]
DREF SREF Input Dn Output Sn Transistor
HH0VXXoff
HHV
TT
[4]
HV
TT
[2]
[4]
on
HHV
TT
[4]
LL
[3]
on
LL0V V
TT
[4]
XXoff
Table 5. Function selection, LOW to HIGH translation
Assuming Dn is at the higher voltage level.
H = HIGH voltage level; L = LOW voltage level; X = Don’t care.
GREF
[1]
DREF SREF Input Sn Output Dn Transistor
HH0VXXoff
HHV
TT
[4]
V
TT
[4]
H
[2]
nearly off
HHV
TT
[4]
LL
[3]
on
LL0V V
TT
[4]
XXoff