Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Transducer Converter, Bidirectional TSSOP 14

1. General description

The GTL2005 is a quad translating transceiver designed for 3.3 V system interface with a

GTL/GTL+ bus.

The direction pin (DIR) allows the part to function as either a GTL-to-TTL sampling

receiver or as a TTL-to-GTL interface.

The GTL2005 LVTTL interface is tolerant up to 5.5 V allowing direct access to TTL or 5 V

CMOS outputs.

The GTL2005 V

ref

linearity degrades below 0.8 V (see Section 10.1). If the application

allows, use the GTL2014, otherwise more closely review noise margins.

2. Features

n Operates as a quad GTL/GTL+ sampling receiver or as a LVTTL/TTL to GTL/GTL+

driver

n Quad bidirectional bus interface

n 3.0 V to 3.6 V operation with 5 V tolerant LVTTL I/O

n Live insertion/extraction permitted

n Latch-up protection exceeds 500 mA per JESD78

n ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per

JESD22-A115, and 1000 V CDM per JESD22-CC101

n Package offered: TSSOP14

GTL2005

Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched

translator

Rev. 07 — 3 February 2009 Product data sheet

Fig 1. GTL2005/GTL2014 positioning

002aab378

GTL−

GTL

GTL+

fast t

slow t

GTL2014

GTL2005

Summary of content (19 pages)

PAGE 1
GTL2005 Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator Rev. 07 — 3 February 2009 Product data sheet 1. General description The GTL2005 is a quad translating transceiver designed for 3.3 V system interface with a GTL/GTL+ bus. The direction pin (DIR) allows the part to function as either a GTL-to-TTL sampling receiver or as a TTL-to-GTL interface. The GTL2005 LVTTL interface is tolerant up to 5.5 V allowing direct access to TTL or 5 V CMOS outputs.
PAGE 2
GTL2005 NXP Semiconductors Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator 3. Quick reference data Table 1. Quick reference data VCC = 3.3 V ± 0.3 V Symbol Parameter Conditions Min Typ[1] Max Unit Ci input capacitance control inputs; VI = 3.0 V or 0 V - 2.3 3.5 pF Cio input/output capacitance A port; VO = VTT or 0 V - 3.4 5.0 pF B port; VO = 3.0 V or 0 V - 6.0 7.0 pF - 2.1 2.3 ns - 1.9 2.6 ns - 4.1 5.9 ns - 4.4 5.9 ns GTL; Vref = 0.
PAGE 3
GTL2005 NXP Semiconductors Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator 5. Functional diagram GTL2005 A0 B0 A1 B1 A2 B2 A3 B3 002aab151 VREF Fig 2. DIR Logic diagram of GTL2005 6. Pinning information 6.1 Pinning DIR 1 14 VCC A0 2 13 B0 A1 3 VREF 4 A2 5 10 B2 A3 6 9 B3 GND 7 8 GND 12 B1 GTL2005PW 11 GND 002aab150 Fig 3. Pin configuration for TSSOP14 GTL2005_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev.
PAGE 4
GTL2005 NXP Semiconductors Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator 6.2 Pin description Table 3. Pin description Symbol Pin Description DIR 1 direction control input A0 2 data inputs/outputs (A side, GTL) A1 3 A2 5 A3 6 B0 13 B1 12 B2 10 B3 9 VREF 4 GTL reference voltage GND 7, 8, 11 ground (0 V) VCC 14 positive supply voltage data inputs/outputs (B side, TTL) 7. Functional description Refer to Figure 2 “Logic diagram of GTL2005”. 7.
PAGE 5
GTL2005 NXP Semiconductors Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min VCC DC supply voltage IIK VI Unit −0.5 +4.6 V DC input diode current VI < 0 V - −50 mA DC input voltage A port −0.5[2] +7.0 V B port −0.5[2] +4.
PAGE 6
GTL2005 NXP Semiconductors Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator 9. Recommended operating conditions Table 6. Operating conditions [1] Symbol Parameter Conditions VCC supply voltage VTT termination voltage reference voltage Vref input voltage VI HIGH-level input voltage VIH LOW-level input voltage VIL Min Typ Max Unit 3.0 3.3 3.6 V GTL− 0.85 0.9 0.95 V GTL 1.14 1.2 1.26 V GTL+ 1.35 1.5 1.65 V 0.5 2⁄ V 3 TT 1.8 V GTL− 0.5 0.6 0.
PAGE 7
GTL2005 NXP Semiconductors Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator 10. Static characteristics Table 7. Static characteristics Recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = −40 °C to +85 °C. Symbol VOH Parameter HIGH-level output voltage LOW-level output voltage VOL input current II Min Typ[1] Max Unit B port; VCC = 3.0 V to 3.6 V; IOH = −100 µA [2] VCC − 0.2 - - V B port; VCC = 3.0 V; IOH = −12 mA [2] 2.
PAGE 8
GTL2005 NXP Semiconductors Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator 10.1 Performance curves 002aab152 1200 VTH+ and VTH− (mV) 1000 002aab153 1200 VTH+ and VTH− (mV) 1000 VTH+ VTH+ VTH− 800 Vref 800 VTH− 600 Vref 600 400 0.5 0.6 0.7 0.9 0.8 400 0.5 1.0 Vref (V) a. VCC = 3.0 V 0.6 0.7 0.8 0.9 1.0 Vref (V) b. VCC = 3.3 V 002aab154 1200 VTH+ and VTH− (mV) 1000 VTH+ 800 Vref VTH− 600 400 0.5 0.6 0.7 0.8 0.9 1.0 Vref (V) c. VCC = 3.6 V Fig 4.
PAGE 9
GTL2005 NXP Semiconductors Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator 002aab155 1200 VTH+ and VTH− (mV) 1000 002aab156 1200 VTH+ and VTH− (mV) 1000 VTH+ VTH+ Vref Vref VTH− 800 800 600 600 400 0.5 0.6 0.7 0.9 0.8 400 0.5 1.0 Vref (V) a. VCC = 3.0 V 0.6 0.7 VTH− 0.8 0.9 1.0 Vref (V) b. VCC = 3.3 V 002aab157 1200 VTH+ and VTH− (mV) 1000 VTH+ Vref VTH− 800 600 400 0.5 0.6 0.7 0.8 0.9 1.0 Vref (V) c. VCC = 3.6 V Fig 5.
PAGE 10
GTL2005 NXP Semiconductors Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator 002aab158 1200 VTH+ and VTH− (mV) 1000 002aab159 1200 VTH+ and VTH− (mV) 1000 VTH+ VTH− VTH+ 800 800 VTH− Vref 600 600 Vref 400 0.5 0.6 0.7 0.9 0.8 400 0.5 1.0 Vref (V) a. VCC = 3.0 V 0.6 0.7 0.8 0.9 1.0 Vref (V) b. VCC = 3.3 V 002aab160 1200 VTH+ and VTH− (mV) 1000 VTH+ 800 VTH− Vref 600 400 0.5 0.6 0.7 0.8 0.9 1.0 Vref (V) c. VCC = 3.6 V Fig 6.
PAGE 11
GTL2005 NXP Semiconductors Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator 11. Dynamic characteristics Table 8. Dynamic characteristics VCC = 3.3 V ± 0.3 V Symbol Parameter Conditions Min Typ[1] Max Unit see Figure 7 - 2.1 2.3 ns - 1.9 2.6 ns - 4.1 5.9 ns - 4.4 5.9 ns - 2.1 2.3 ns - 1.9 2.6 ns - 4.1 5.9 ns - 4.4 5.9 ns - 2.1 2.3 ns - 1.9 2.6 ns - 4.2 5.7 ns - 3.8 5.4 ns GTL−; Vref = 0.
PAGE 12
GTL2005 NXP Semiconductors Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator 3.0 V input Vref Vref 0V tPLH tPHL VOH 1.5 V output 1.5 V VOL 002aab163 PRR ≤ 10 MHz; Zo = 50 Ω; tr ≤ 2.5 ns; tf ≤ 2.5 ns Fig 8. Propagation delay, An to Bn 12. Test information VCC PULSE GENERATOR VI VO DUT RL 500 Ω CL 50 pF RT 002aab006 Fig 9. Load circuitry for switching times VTT VCC PULSE GENERATOR VI 25 Ω VO DUT CL 30 pF RT 002aab143 Fig 10.
PAGE 13
GTL2005 NXP Semiconductors Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator 13. Package outline TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.
PAGE 14
GTL2005 NXP Semiconductors Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits.
PAGE 15
GTL2005 NXP Semiconductors Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator 14.
PAGE 16
GTL2005 NXP Semiconductors Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 12. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 15. Abbreviations Table 11.
PAGE 17
GTL2005 NXP Semiconductors Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator 16. Revision history Table 12.
PAGE 18
GTL2005 NXP Semiconductors Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
PAGE 19
GTL2005 NXP Semiconductors Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator 19. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 10.1 11 11.1 12 13 14 14.1 14.2 14.3 14.4 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . .