Datasheet
1. General description
The HEF4014B is a fully synchronous edge-triggered 8-bit static shift register with eight
synchronous parallel inputs (D0 to D7), a synchronous serial data input (DS), a
synchronous parallel enable input (PE), a LOW-to-HIGH edge-triggered clock input (CP)
and buffered parallel outputs from the last three stages (Q5 to Q7).
Operation is synchronous and the device is edge-triggered on the LOW-to-HIGH
transition of CP. Each register stage is of a D-type master-slave flip-flop type. When PE is
HIGH, data is loaded into the register from D0 to D7 on the LOW-to-HIGH transition of CP.
When PE is LOW, data is shifted to the first position from DS, and all the data in the
register is shifted one position to the right on the LOW-to-HIGH transition of CP. The clock
input’s Schmitt trigger action makes it highly tolerant of slower clock rise and fall times.
It operates over a recommended V
DD
power supply range of 3 V to 15 V referenced to V
SS
(usually ground). Unused inputs must be connected to V
DD
, V
SS
, or another input.
2. Features and benefits
Tolerant of slow clock rise and fall times
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +85 C
Complies with JEDEC standard JESD 13-B
3. Applications
Parallel-to-serial converter
Serial data queueing
General purpose register
4. Ordering information
HEF4014B
8-bit static shift register
Rev. 8 — 21 November 2011 Product data sheet
Table 1. Ordering information
All types operate from
40
C to +85
C
Type number Package
Name Description Version
HEF4014BP DIP16 plastic dual in-line package; 16-leads (300 mil) SOT38-4
HEF4014BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1