Datasheet

HEF4014B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 8 — 21 November 2011 3 of 14
NXP Semiconductors
HEF4014B
8-bit static shift register
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 3. Pin configuration DIP16 and SO16
HEF4014B
D7 V
DD
Q5 D6
Q7 D5
D3 D4
D2 Q6
D1 DS
D0 CP
V
SS
PE
001aae557
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
Table 2. Pin description
Symbol Pin Description
Q5 to Q7 2, 12, 3 output
D0 to D7 7, 6, 5, 4, 13, 14, 15, 1 parallel data input
V
SS
8 ground supply voltage
PE 9 parallel enable input
CP 10 clock input (LOW-to-HIGH edge-triggered)
DS 11 serial data input
V
DD
16 supply voltage