Datasheet

1. General description
The HEF40175B is a quad edge-triggered D-type flip-flop with four data inputs (D0 to D3),
a clock input (CP), an overriding asynchronous master reset input (MR
), four buffered
outputs (Q0 to Q3), and four complementary buffered outputs (Q
0 to Q3). Information on
D0 to D3 is transferred to Q0 to Q3 on the LOW-to-HIGH transition of CP if MR
is HIGH.
When LOW, MR
resets all flip-flops (Q0 to Q3 = LOW; Q0 to Q3 = HIGH), independent of
CP and D0 to D3.
It operates over a recommended V
DD
power supply range of 3 V to 15 V referenced to V
SS
(usually ground). Unused inputs must be connected to V
DD
, V
SS
, or another input.
2. Features and benefits
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +125 C
Complies with JEDEC standard JESD 13-B
3. Applications
Shift registers
Buffer/storage register
Pattern generator
4. Ordering information
HEF40175B
Quad D-type flip-flop
Rev. 8 — 21 November 2011 Product data sheet
Table 1. Ordering information
All types operate from 40 C to +125 C.
Type number Package
Name Description Version
HEF40175BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
HEF40175BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
HEF40175BTT TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

Summary of content (15 pages)