Datasheet

1. General description
The HEF4027B is a edge-triggered dual JK flip-flop which features independent set-direct
(SD), clear-direct (CD), clock (CP) inputs and outputs (Q, Q
). Data is accepted when CP is
LOW, and transferred to the output on the positive-going edge of the clock. The active
HIGH asynchronous clear-direct (CD) and set-direct (SD) inputs are independent and
override the J, K, and CP inputs. The outputs are buffered for best system performance.
Schmitt trigger action makes the clock input highly tolerant of slower rise and fall times.
It operates over a recommended V
DD
power supply range of 3 V to 15 V referenced to V
SS
(usually ground). Unused inputs must be connected to V
DD
, V
SS
, or another input.
2. Features and benefits
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +85 C
Complies with JEDEC standard JESD 13-B
3. Applications
Registers
Counters
Control circuits
4. Ordering information
HEF4027B
Dual JK flip-flop
Rev. 9 — 18 November 2011 Product data sheet
Table 1. Ordering information
T
amb
from
40
C to +85
C.
Type number Package
Name Description Version
HEF4027BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
HEF4027BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Summary of content (14 pages)