Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Gate and inverter XOR gate 4000B SO 14

1. General description

The HEF4030B is a quad 2-input EXCLUSIVE-OR gate. The outputs are fully buffered for

the highest noise immunity and pattern insensitivity to output impedance.

It operates over a recommended V

power supply range of 3 V to 15 V referenced to V

(usually ground). Unused inputs must be connected to V

, V

, or another input.

2. Features and benefits

 Fully static operation

 5 V, 10 V, and 15 V parametric ratings

 Standardized symmetrical output characteristics

 Specified from 40 C to +125 C

 Complies with JEDEC standard JESD 13-B

 Inputs and outputs are protected against electrostatic effects

3. Ordering information

4. Functional diagram

HEF4030B

Quad 2-input EXCLUSIVE-OR gate

Rev. 4 — 13 November 2013 Product data sheet

Table 1. Ordering information

All types operate from





C to +125



Type number Package

Name Description Version

HEF4030BP DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1

HEF4030BT SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

Fig 1. Functional diagram Fig 2. Logic diagram (one gate)

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Summary of content (12 pages)

PAGE 1
HEF4030B Quad 2-input EXCLUSIVE-OR gate Rev. 4 — 13 November 2013 Product data sheet 1. General description The HEF4030B is a quad 2-input EXCLUSIVE-OR gate. The outputs are fully buffered for the highest noise immunity and pattern insensitivity to output impedance. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. 2.
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HEF4030B NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate 5. Pinning information 5.1 Pinning +() % $ 9'' % % < $ < < $ < % % 966 $ DDD Fig 3. Pin configuration 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A, 2A, 3A, 4A 1, 5, 8, 12 data input 1B, 2B, 3B, 4B 2, 6, 9, 13 data input 1Y, 2Y, 3Y, 4Y 3, 4, 10, 11 data output VSS 7 ground (0 V) VDD 14 supply voltage 6.
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HEF4030B NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground). Symbol Parameter VDD supply voltage Conditions Min 0.5 VI < 0.5 V or VI > VDD + 0.
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HEF4030B NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate 9. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD; unless otherwise specified. Symbol Parameter VIH VIL VOH VOL IOH IOL HIGH-level input voltage LOW-level input voltage Min Max Min Max Min Max 5V 3.5 - 3.5 - 3.5 - 3.5 - V 10 V 7.0 - 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 - 3.
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HEF4030B NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate 10. Dynamic characteristics Table 7. Dynamic characteristics Tamb = 25 C; for waveforms see Figure 4; for test circuit, see Figure 5; unless otherwise specified. Symbol Parameter HIGH to LOW propagation delay tPHL LOW to HIGH propagation delay tPLH VDD Min Typ Max Unit 57 + 0.55  CL 5V - 85 175 ns 24 + 0.23  CL 10 V - 35 75 ns 22 + 0.16  CL 15 V - 30 55 ns 47 + 0.55  CL 5V - 75 150 ns 19 + 0.
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HEF4030B NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate 11. Waveforms WU 9, WI 90 Q$ Q% LQSXW 9 W3+/ 92+ W3/+ 90 Q< RXWSXW 92/ W7+/ W7/+ DDD Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 4. Input to output propagation delays and output transition times Table 9. Measurement points Supply voltage Input Output VDD VM VM 5 V to 15 V 0.5VDD 0.
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HEF4030B NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate 12. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b MH 8 14 pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.
PAGE 8
HEF4030B NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.
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HEF4030B NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate 13. Abbreviations Table 11. Abbreviations Acronym Description DUT Device Under Test 14. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4030B v.4 20131113 Product data sheet - HEF4030B_CNV v.3 Modifications: HEF4030B_CNV v.
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HEF4030B NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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HEF4030B NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
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HEF4030B NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . .