Datasheet

HEF4030B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 13 November 2013 6 of 12
NXP Semiconductors
HEF4030B
Quad 2-input EXCLUSIVE-OR gate
11. Waveforms
Measurement points are given in Table 9.
Logic levels: V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 4. Input to output propagation delays and output transition times
DDD
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Q<RXWSXW
W
3/+
W
3+/
9
9
,
9
0
9
0
9
2+
9
2/
W
7+/
W
7/+




W
U
W
I
Table 9. Measurement points
Supply voltage Input Output
V
DD
V
M
V
M
5 V to 15 V 0.5V
DD
0.5V
DD
Test data is given in Table 10.
Definitions for test circuit:
DUT = Device Under Test.
C
L
= load capacitance including jig and probe capacitance.
R
T
= termination resistance should be equal to the output impedance Z
o
of the pulse generator.
Fig 5. Test circuit for measuring switching times
V
DD
V
I
V
O
001aag182
DUT
C
L
R
T
G
Table 10. Test data
Supply voltage Input Load
V
DD
V
I
t
r
, t
f
C
L
5 V to 15 V V
SS
or V
DD
 20 ns 50 pF