Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Latch SR latch Three-state SO 16

1. General description

The HEF4043B is a quad R/S latch with 3-state outputs with a common output enable

input (OE). Each latch has an active HIGH set input (1S to 4S), an active HIGH reset input

(1R to 4R) and an active HIGH 3-state output (1Q to 4Q).

When OE is HIGH, the latch output (nQ) is determined by the nR and nS inputs as shown

in Table 3

. When OE is LOW, the latch outputs are in the high impedance OFF-state. OE

does not affect the state of the latch. The high impedance off-state feature allows common

bussing of the outputs.

It operates over a recommended V

power supply range of 3 V to 15 V referenced to V

(usually ground). Unused inputs must be connected to V

, V

, or another input.

2. Features and benefits

 Fully static operation

 5 V, 10 V, and 15 V parametric ratings

 Standardized symmetrical output characteristics

 Specified from 40 C to +85 C

 Complies with JEDEC standard JESD 13-B

3. Applications

 Four-bit storage with output enable

4. Ordering information

HEF4043B

Quad R/S latch with 3-state outputs

Rev. 10 — 18 November 2011 Product data sheet

Table 1. Ordering information

All types operate from





C to +85



Type number Package

Name Description Version

HEF4043BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4

HEF4043BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Summary of content (14 pages)

PAGE 1
HEF4043B Quad R/S latch with 3-state outputs Rev. 10 — 18 November 2011 Product data sheet 1. General description The HEF4043B is a quad R/S latch with 3-state outputs with a common output enable input (OE). Each latch has an active HIGH set input (1S to 4S), an active HIGH reset input (1R to 4R) and an active HIGH 3-state output (1Q to 4Q). When OE is HIGH, the latch output (nQ) is determined by the nR and nS inputs as shown in Table 3.
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HEF4043B NXP Semiconductors Quad R/S latch with 3-state outputs 5. Functional diagram 4 1S 1Q 2 3 1R 6 2S 2Q 9 7 2R 12 3S 3-STATE OUTPUTS nS nQ 3Q 10 11 3R nR 14 4S 4Q 1 15 4R OE 5 OE to other latches 001aae618 001aae616 Fig 1. Functional diagram Fig 2. Logic diagram for one latch 6. Pinning information 6.1 Pinning HEF4043B 4Q 1 16 VDD 1Q 2 15 4R 1R 3 14 4S 1S 4 13 n.c. OE 5 12 3S 2S 6 11 3R 2R 7 10 3Q VSS 8 9 2Q 001aae617 Fig 3.
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HEF4043B NXP Semiconductors Quad R/S latch with 3-state outputs 6.2 Pin description Table 2. Pin description Symbol Pin Description 1Q to 4Q 2, 9, 10, 1 3-state buffered latch output 1R to 4R 3, 7, 11, 15 reset input (active HIGH) 1S to 4S 4, 6, 12, 14 set input (active HIGH) OE 5 common output enable input VSS 8 ground supply voltage n.c. 13 not connected VDD 16 supply voltage 7. Functional description Table 3.
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HEF4043B NXP Semiconductors Quad R/S latch with 3-state outputs 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VDD Conditions Min Typ Max Unit supply voltage 3 - 15 V VI input voltage 0 - VDD V Tamb ambient temperature in free air 40 - +85 C t/V input transition rise and fall rate VDD = 5 V - - 3.75 s/V VDD = 10 V - - 0.5 s/V VDD = 15 V - - 0.08 s/V 10. Static characteristics Table 6.
PAGE 5
HEF4043B NXP Semiconductors Quad R/S latch with 3-state outputs Table 6. Static characteristics …continued VSS = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter IDD supply current Conditions IO = 0 A VDD 5V Tamb = 85 C Unit Min Max Min Max Min Max - 20 - 20 - 150 A 10 V - 40 - 40 - 300 A 15 V - 80 - 80 - 600 A - - - 7.5 - - pF input capacitance CI Tamb = 40 C Tamb = 25 C 11. Dynamic characteristics Table 7.
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HEF4043B NXP Semiconductors Quad R/S latch with 3-state outputs Table 8. Dynamic power dissipation PD PD can be calculated from the formulas shown. VSS = 0 V; tr = tf  20 ns; Tamb = 25 C.
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HEF4043B NXP Semiconductors Quad R/S latch with 3-state outputs VDD OE input VSS tPLZ output LOW-to-OFF OFF-to-LOW tPZL VDD VY VX VSS tPHZ VDD tPZH VY output HIGH-to-OFF OFF-to-HIGH VX VSS outputs on outputs off outputs on 001aag355 Measurement points are given in Table 9. Fig 5. Output enable (OE) to latch output (nQ) enable time (tPZL and tPZH) and disable time (tPLZ and tPHZ) Table 9. Measurement points Supply voltage Input VDD VI VM VM VX VY 5 V to 15 V VDD or 0 V 0.
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HEF4043B NXP Semiconductors Quad R/S latch with 3-state outputs tW VI 90 % 90 % negative pulse VM VM 10 % 0V 10 % tf tr tr tf VI 90 % positive pulse 90 % VM VM 10 % 0V 10 % tW 001aaj781 a. Input waveform VEXT VDD VI RL VO G DUT RT CL 001aaj915 b. Test circuit Test and measurement data is given in Table 10. Definitions test circuit: DUT = Device Under Test. RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
PAGE 9
HEF4043B NXP Semiconductors Quad R/S latch with 3-state outputs 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 1.25 0.85 0.36 0.23 19.50 18.
PAGE 10
HEF4043B NXP Semiconductors Quad R/S latch with 3-state outputs SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.
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HEF4043B NXP Semiconductors Quad R/S latch with 3-state outputs 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4043B v.10 20111118 Product data sheet - HEF4043B v.9 Modifications: • Table 6: IOH minimum values changed to maximum HEF4043B v.9 20091216 Product data sheet - HEF4043B v.8 HEF4043B v.8 20091127 Product data sheet - HEF4043B v.7 HEF4043B v.7 20090710 Product data sheet - HEF4043B v.
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HEF4043B NXP Semiconductors Quad R/S latch with 3-state outputs 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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HEF4043B NXP Semiconductors Quad R/S latch with 3-state outputs Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.
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HEF4043B NXP Semiconductors Quad R/S latch with 3-state outputs 17. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . .