HEF4046B Phase-locked loop Rev. 5 — 18 November 2011 Product data sheet 1. General description The HEF4046B is a phase-locked loop circuit that consists of a linear Voltage Controlled Oscillator (VCO) and two different phase comparators with a common signal input amplifier and a common comparator input. A 7 V regulator (Zener) diode is provided for supply voltage regulation if necessary. For a functional description see Section 6.
HEF4046B NXP Semiconductors Phase-locked loop 4. Functional diagram PHASE COMPARATOR 1 SIG_IN 14 2 PC1_OUT COMP_IN 3 13 PC2_OUT PHASE COMPARATOR 2 ÷N R3 1 PCP 9 VCO_IN VCO_OUT 4 LOW-PASS FILTER C1A 6 C1 C2 VCO VSS R1 R1 11 R2 R2 12 10 SF_OUT SOURCE FOLLOWER C1B 7 VSS RSF VSS INH 5 VSS (pin 8) 15 ZENER 001aae626 Fig 1. Functional diagram 5. Pinning information 5.
HEF4046B NXP Semiconductors Phase-locked loop 5.2 Pin description Table 2.
HEF4046B NXP Semiconductors Phase-locked loop the frequency range of input signals on which the PLL will lock if it was initially out of lock. The frequency lock range (2fL) is defined as the frequency range of input signals on which the loop will stay locked if it was initially in lock. The capture range is smaller or equal to the lock range.
HEF4046B NXP Semiconductors Phase-locked loop Phase comparator 2 is an edge-controlled digital memory network. It consists of four flip-flops, control gating and a 3-state output circuit comprising p and n-type drivers with a common output node. When the p-type or n-type drivers are ON, they pull the output up to VDD or down to VSS respectively. This type of phase comparator only acts on the positive-going edges of the signals at SIG_IN and COMP_IN.
HEF4046B NXP Semiconductors Phase-locked loop Figure 6 shows the state diagram for phase comparator 2. Each circle represents a state of the comparator. The number at the top, inside each circle, represents the state of the comparator, while the logic state of the signal and comparator inputs are represented by a ‘0’ for a logic LOW or a ‘1’ for a logic HIGH, and they are shown in the left and right bottom of each circle.
HEF4046B NXP Semiconductors Phase-locked loop 7. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD supply voltage IIK input clamping current VI input voltage IOK output clamping current II/O Conditions Min Max Unit 0.5 +18 V - 10 mA 0.5 VDD + 0.
HEF4046B NXP Semiconductors Phase-locked loop 9. Static characteristics Table 5. Static characteristics VSS = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter HIGH-level input voltage VIH LOW-level input voltage VIL VOH VOL IOZ OFF-state output current input capacitance Min Max 3.5 - 3.5 - V - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 V 5V 4.95 - 4.95 - 4.
HEF4046B NXP Semiconductors Phase-locked loop 10. Dynamic characteristics Table 6. Dynamic characteristics VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns. Symbol Parameter Conditions VDD Min Typ Max Unit Phase comparators RI Vi(sens) VIL input resistance 5V - 750 - k 10 V - 220 - k 15 V - 140 - k SIG_IN input A.C.
HEF4046B NXP Semiconductors Phase-locked loop Table 6. Dynamic characteristics …continued VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns. Symbol Parameter Conditions f/f relative frequency variation for VCO see Figure 13 and 14 duty factor input resistance Rin VDD Min Typ Max Unit R1 > 10 k 5V - 0.50 - % Hz R1 > 400 k 10 V - 0.25 - % Hz R1 = M 15 V - 0.
HEF4046B NXP Semiconductors Phase-locked loop 11.1 VCO component selection Recommended range for R1 and R2: 10 k to 1 M; for C1: 50 pF to any practical value. 1. VCO without frequency offset (R2 = ). a. Given f0: use f0 with Figure 7 to determine R1 and C1. b. Given fmax: calculate f0 from f0 = 0.5fmax; use f0 with Figure 7 to determine R1 and C1. 2. VCO with frequency offset. a.
HEF4046B NXP Semiconductors Phase-locked loop 001aae634 102 R2 R1 001aae635 105 P (μW) (1) (2) (1) 104 10 (2) (3) (4) 103 1 (5) (6) 10−1 102 10−2 1 10 102 fmax/fmax 103 10 1 10 102 103 R1 (kΩ) Line (1): VDD = 5 V; R2 = ; VCO_IN at 0.5VDD; CL = 50 pF. Line (2): VDD = 10 V, 15 V. Lines (1) and (2): VDD = 15 V; Lines (3) and (4): VDD = 10 V; Lines (5) and (6): VDD = 5 V; Lines (1), (3), and (5): C1 = 50 pF; Lines (2), (4), and (6): C1 = 1 F. Fig 9.
HEF4046B NXP Semiconductors Phase-locked loop f fmax f2 fo fo ' f1 ΔV ΔV 1/2VDD VDD VVCO IN 001aae638 See Section 10. For VCO linearity: f1 + f2 f 0 = -------------2 f 0 – f 0 linearity = ---------------- 100 % f 0 This figure and the above formula also apply to source follower linearity: substitute VO at SF_OUT for f. V = 0.3 V at VDD = 5 V; V = 2.5 V at VDD = 10 V; V = 5.0 V at VDD = 15 V. Fig 13.
HEF4046B NXP Semiconductors Phase-locked loop 001aae639 0.5 001aae640 5 (1) lin (%) lin (%) (2) 0 (1) 0 (2) (3) (3) (4) (4) −0.5 −1 −5 10 102 −10 103 102 10 R1 (kΩ) 103 R1 (kΩ) a. VDD = 5 V b. VDD = 10 V 001aae641 5 lin (%) (1) 0 (2) (3) (4) −5 −10 102 10 103 R1 (kΩ) c. VDD = 15 V R2 = ; Line (1): C1 = 1 F; Line (2): C1 = 1 nF; Line (3): C1 = 100 pF; Line (4): C1 = 50 pF. Fig 14.
HEF4046B NXP Semiconductors Phase-locked loop 12. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 1.25 0.85 0.36 0.23 19.50 18.55 6.48 6.20 2.
HEF4046B NXP Semiconductors Phase-locked loop SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.
HEF4046B NXP Semiconductors Phase-locked loop 13. Revision history Table 8. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4046B v.5 20111118 Product data sheet - HEF4046B v.4 Modifications: • • • Section Applications removed Table 5: IOH minimum values changed to maximum Table 6: Rin typical value changed from 106 M to 10 M HEF4046B v.4 20100105 Product data sheet - HEF4046B_CNV v.3 HEF4046B_CNV v.
HEF4046B NXP Semiconductors Phase-locked loop 14. Legal information 14.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
HEF4046B NXP Semiconductors Phase-locked loop Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.
HEF4046B NXP Semiconductors Phase-locked loop 16. Contents 1 2 3 4 5 5.1 5.2 6 6.1 6.2 7 8 9 10 11 11.1 12 13 14 14.1 14.2 14.3 14.4 15 16 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . .