Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Inverter Inverter 4000B SO 14

1. General description

The HEF4069UB is a general purpose hex inverter. Each inverter has a single stage.

It operates over a recommended V

power supply range of 3 V to 15 V referenced to V

(usually ground). Unused inputs must be connected to V

, V

, or another input.

2. Features and benefits

 Fully static operation

 5 V, 10 V, and 15 V parametric ratings

 Standardized symmetrical output characteristics

 Specified from 40 C to +85 C and 40 C to +125 C

 Complies with JEDEC standard JESD 13-B

3. Applications

 Oscillator

4. Ordering information

HEF4069UB

Hex inverter

Rev. 8 — 16 November 2011 Product data sheet

Table 1. Ordering information

All types operate from





C to +125



Type number Package

Name Description Version

HEF4069UBP DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1

HEF4069UBT SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

HEF4069UBTT TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

Summary of content (17 pages)

PAGE 1
HEF4069UB Hex inverter Rev. 8 — 16 November 2011 Product data sheet 1. General description The HEF4069UB is a general purpose hex inverter. Each inverter has a single stage. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. 2.
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HEF4069UB NXP Semiconductors Hex inverter 5. Functional diagram 1A 2A 3A 4A 5A 6A 1 2 3 4 5 6 9 8 11 10 13 12 1Y 2Y 3Y 4Y VDD 5Y A 6Y VSS 001aag154 001aag152 Fig 1. Y Functional diagram Fig 2. Schematic diagram (one inverter) 6. Pinning information 6.1 Pinning 1A 1 14 VDD 1Y 2 13 6A 2A 3 12 6Y 2Y 4 HEF4069UB 11 5A 3A 5 10 5Y 3Y 6 9 4A VSS 7 8 4Y 001aag153 Fig 3. Pin configuration 6.2 Pin description Table 2.
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HEF4069UB NXP Semiconductors Hex inverter 7. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD supply voltage IIK input clamping current VI input voltage IOK output clamping current II/O Conditions Min Max 0.5 VI < 0.5 V or VI > VDD + 0.5 V 0.5 +18 V 10 mA VDD + 0.
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HEF4069UB NXP Semiconductors Hex inverter 9. Static characteristics Table 5. Static characteristics VSS = 0 V; VI = VSS or VDD; unless otherwise specified.
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HEF4069UB NXP Semiconductors Hex inverter 10. Dynamic characteristics Table 6. Dynamic characteristics Tamb = 25 C; for waveforms see Figure 4; for test circuit see Figure 5. Symbol Parameter HIGH to LOW propagation delay tPHL tPLH tTHL [1] nA to nY; LOW to HIGH propagation delay nA to nY HIGH to LOW output transition time output nY LOW to HIGH output transition time tTLH Conditions output nY Extrapolation formula[1] Min Typ Max 5V 18 ns + (0.
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HEF4069UB NXP Semiconductors Hex inverter 11. Waveforms tr VI 90 % VM input 0V tf 10 % tPHL VOH tPLH 90 % VM output 10 % VOL tTLH 001aag185 tTHL Measurement points: VM = 0.5VDD. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 4.
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HEF4069UB NXP Semiconductors Hex inverter 11.1 Transfer characteristics 001aag159 5.0 500 VO (V) 250 (2) (1) 0 ID (mA) 5 5 (2) (2) 0 5.0 0 2.5 10 VO (V) ID (μA) 2.5 001aag160 10 (1) (2) 0 0 0 5 VI (V) 10 VI (V) a. VDD = 5 V; IO = 0 A b. VDD = 10 V; IO = 0 A 001aag161 20 20 VO (V) ID (mA) 10 10 (2) (1) (2) 0 0 0 10 20 VI (V) c. VDD = 15 V; IO = 0 A (1) VO = output voltage. (2) ID = drain current. Fig 6.
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HEF4069UB NXP Semiconductors Hex inverter 12. Application information Some examples of applications for the HEF4069UB. Figure 7 shows an astable relaxation oscillator using two HEF4069UB inverters and 2 BAW62 diodes. The oscillation frequency is mainly determined by R1  C1, provided R1 << R2 and R2  C2 << R1  C1. The function of R2 is to minimize the influence of the forward voltage across the protection diodes on the frequency; C2 is a stray (parasitic) capacitance.
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HEF4069UB NXP Semiconductors Hex inverter Figure 8 shows a crystal oscillator for frequencies up to 10 MHz using two HEF4069UB inverters. The second inverter amplifies the oscillator output voltage to a level sufficient to drive other Local Oxidation CMOS (LOCMOS) circuits. 22 pF 1 MΩ 1 MΩ 2 MHz 2.2 kΩ 100 pF 22 pF 1/6 HEF4069UB 1/6 HEF4069UB 001aag155 The output inverter is used to amplify the oscillator output voltage to a level sufficient to drive other LOCMOS circuits. Fig 8.
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HEF4069UB NXP Semiconductors Hex inverter Figure 12 shows typical forward transconductance and Figure 13 shows the test set-up. 001aag164 10 gfs (mA/V) (1) 7.5 (2) Rbias = 560 kΩ 5.0 (3) VDD 2.5 0.47 μF input output Vi 0 0 5 10 100 μF A Io VSS 15 VDD (V) 001aag163 (1) Average +2; where: ‘’ is the standard deviation. (2) Average. (3) Average 2; where: ‘’ is the standard deviation. dI g fs = -------o- at VO is constant. dV i fi.= 1 kHz Fig 12.
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HEF4069UB NXP Semiconductors Hex inverter 13. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b MH 8 14 pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.
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HEF4069UB NXP Semiconductors Hex inverter SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.
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HEF4069UB NXP Semiconductors Hex inverter TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.
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HEF4069UB NXP Semiconductors Hex inverter 14. Revision history Table 9. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4069UB v.8 20111116 Product data sheet - HEF4069UB v.7 Modifications: • • Legal pages updated. Changes in “General description”, “Features and benefits” and “Applications”. HEF4069UB v.7 20110511 Product data sheet - HEF4069UB v.6 HEF4069UB v.6 20091208 Product data sheet - HEF4069UB v.5 HEF4069UB v.
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HEF4069UB NXP Semiconductors Hex inverter 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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HEF4069UB NXP Semiconductors Hex inverter Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.
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HEF4069UB NXP Semiconductors Hex inverter 17. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 11.1 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . .