Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Gate AND gate 4000B SO 14

1. General description

The HEF4081B is a quad 2-input AND gate. The outputs are fully buffered for highest

noise immunity and pattern insensitivity to output impedance variations.

It operates over a recommended V

power supply range of 3 V to 15 V referenced to V

(usually ground). Unused inputs must be connected to V

, V

, or another input.

2. Features and benefits

 Fully static operation

 5 V, 10 V, and 15 V parametric ratings

 Standardized symmetrical output characteristics

 Inputs and outputs are protected against electrostatic effects

 Specified from40 C to +85 C and 40 C to +125 C

 Complies with JEDEC standard JESD 13-B

3. Ordering information

4. Functional diagram

HEF4081B

Quad 2-input AND gate

Rev. 7 — 16 November 2011 Product data sheet

Table 1. Ordering information

All types operate from





C to +125



Type number Package

Name Description Version

HEF4081BP DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1

HEF4081BT SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

Fig 1. Functional diagram Fig 2. Logic diagram (one gate)

001aai139

001aag180

Summary of content (12 pages)

PAGE 1
HEF4081B Quad 2-input AND gate Rev. 7 — 16 November 2011 Product data sheet 1. General description The HEF4081B is a quad 2-input AND gate. The outputs are fully buffered for highest noise immunity and pattern insensitivity to output impedance variations. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. 2.
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HEF4081B NXP Semiconductors Quad 2-input AND gate 5. Pinning information 5.1 Pinning 1A 1 14 VDD 1B 2 13 4B 1Y 3 12 4A 2Y 4 2A 5 2B 6 VSS 7 HEF4081B 11 4Y 10 3Y 9 3B 8 3A 001aag178 Fig 3. Pin configuration 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A to 4A 1, 5, 8, 12 input 1B to 4B 2, 6, 9, 13 input 1Y to 4Y 3, 4, 10, 11 output VSS 7 ground (0 V) VDD 14 supply voltage 6. Functional description Table 3.
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HEF4081B NXP Semiconductors Quad 2-input AND gate 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
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HEF4081B NXP Semiconductors Quad 2-input AND gate Table 6. Static characteristics …continued VSS = 0 V; VI = VSS or VDD; unless otherwise specified. Symbol Parameter VOH VOL IOH IOL HIGH-level output voltage IO < 1 A VDD Tamb = 40 C Tamb = +25 C Tamb = +85 C Tamb = +125 C Unit Min Max Min Max Min Max Min Max 4.95 - 4.95 - 4.95 - 4.95 - V 10 V 9.95 - 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - 14.95 - V 5V - 0.05 - 0.05 - 0.05 - 0.
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HEF4081B NXP Semiconductors Quad 2-input AND gate 10. Dynamic characteristics Table 7. Dynamic characteristics Tamb = 25 C; for waveforms see Figure 4; for test circuit see Figure 5; unless otherwise specified. [1] Symbol Parameter HIGH to LOW propagation delay tPHL LOW to HIGH propagation delay tPLH Conditions VDD nA or nB to nY nA or nB to nY Extrapolation formula Min Typ Max Unit 5V 28 ns + (0.55 ns/pF)CL - 55 110 ns 10 V 15 V 14 ns + (0.23 ns/pF)CL - 25 50 ns 12 ns + (0.
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HEF4081B NXP Semiconductors Quad 2-input AND gate 11. Waveforms tr VI tf 90 % nA, nB input VM 0V 10 % tPLH VOH tPHL 90 % nY output VM VOL 10 % tTLH tTHL 001aai140 Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 4. Input to output propagation delay and output transition times Table 9. Measurement points Supply voltage Input Output VDD VM VM 5 V to 15 V 0.5VDD 0.
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HEF4081B NXP Semiconductors Quad 2-input AND gate 12. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b MH 8 14 pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.
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HEF4081B NXP Semiconductors Quad 2-input AND gate SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.
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HEF4081B NXP Semiconductors Quad 2-input AND gate 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4081B v.7 20111116 Product data sheet - HEF4081B v.6 Modifications: • Table 6: IOH minimum values changed to maximum HEF4081B v.6 20091202 Product data sheet - HEF4081B v.5 HEF4081B v.5 20090629 Product data sheet - HEF4081B v.4 HEF4081B v.4 20080526 Product data sheet - HEF4081B_CNV v.3 HEF4081B_CNV v.
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HEF4081B NXP Semiconductors Quad 2-input AND gate 14. Legal information 14.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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HEF4081B NXP Semiconductors Quad 2-input AND gate Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.
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HEF4081B NXP Semiconductors Quad 2-input AND gate 16. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 14.1 14.2 14.3 14.4 15 16 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . .