Datasheet

LPC1102_1104 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 7 — 26 September 2013 16 of 43
NXP Semiconductors
LPC1102/1104
32-bit ARM Cortex-M0 microcontroller
In Sleep mode, execution of instructions is suspended until either a reset or interrupt
occurs. Peripheral functions continue operation during Sleep mode and may generate
interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses.
7.14.5.3 Deep-sleep mode
In Deep-sleep mode, the chip is in Sleep mode, and in addition all analog blocks are shut
down except for the watchdog oscillator and the BOD circuit, which can be configured to
remain running in Deep-sleep mode to allow a reset initiated by a timer or BOD event.
Deep-sleep mode allows for additional power savings.
Six of the GPIO pins (see Table 3
) serve as external wake-up pins to a dedicated start
logic to wake up the chip from Deep-sleep mode.
The clock source should be switched to IRC before entering Deep-sleep mode unless the
watchdog oscillator remains running in Deep-sleep mode. The IRC can be switched on
and off glitch-free and provides a clean clock signal after start-up.
7.15 System control
7.15.1 Start logic
The start logic connects external pins to corresponding interrupts in the NVIC. Each pin
shown in Table 3
as input to the start logic has an individual interrupt in the NVIC interrupt
vector table. The start logic pins can serve as external interrupt pins when the chip is
running. In addition, an input signal on the start logic pins can wake up the chip from
Deep-sleep mode when all clocks are shut down.
The start logic must be configured in the system configuration block and in the NVIC
before being used.
7.15.2 Reset
Reset has four sources on the LPC1102/1104: the RESET pin, the Watchdog reset,
Power-On Reset (POR), and the BrownOut Detection (BOD) circuit. In addition, there is
an ARM software reset. The RESET
pin is a Schmitt trigger input pin. Assertion of chip
reset by any source, once the operating voltage attains a usable level, starts the IRC and
initializes the flash controller.
A LOW-going pulse as short as 50 ns resets the part.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the boot block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
7.15.3 Brownout detection
The LPC1102/1104 include up to four levels for monitoring the voltage on the V
DD
pin. If
this voltage falls below one of the three selected levels, the BOD asserts an interrupt
signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable
Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the
signal by reading a dedicated status register. Four additional threshold levels can be
selected to cause a forced reset of the chip.