Datasheet

LPC1102_1104 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 7 — 26 September 2013 23 of 43
NXP Semiconductors
LPC1102/1104
32-bit ARM Cortex-M0 microcontroller
9.1 BOD static characteristics
[1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see User
manual UM10429.
9.2 Power consumption
Power measurements in Active, Sleep, and Deep-sleep modes were performed under the
following conditions (see user manual UM10429):
• All digital pins configured as GPIO with pull-up resistor disabled in the IOCONFIG
block.
• GPIO pins configured as outputs using the GPIOnDIR registers.
• Write 0 to all GPIOnDATA registers to drive the outputs LOW.
• Write a 1 to bit 4 and bit 5 of the GPIO0DIR register at location 0x5000 8000 and a 0
to bit 4 and bit 5 of the GPIO0DATA register at location 0x5000 3FFC. This ensures
that not-bonded out pins are in a well-defined state.
Table 7. BOD static characteristics
[1]
T
amb
=25  C.
Symbol Parameter Conditions Min Typ Max Unit
V
th
threshold voltage interrupt level 1
assertion - 2.22 - V
de-assertion - 2.35 - V
interrupt level 2
assertion - 2.52 - V
de-assertion - 2.66 - V
interrupt level 3
assertion - 2.80 - V
de-assertion - 2.90 - V
reset level 0
assertion - 1.46 - V
de-assertion - 1.63 - V
reset level 1
assertion - 2.06 - V
de-assertion - 2.15 - V
reset level 2
assertion - 2.35 - V
de-assertion - 2.43 - V
reset level 3
assertion - 2.63 - V
de-assertion - 2.71 - V