Datasheet

LPC1102_1104 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 7 — 26 September 2013 26 of 43
NXP Semiconductors
LPC1102/1104
32-bit ARM Cortex-M0 microcontroller
9.3 CoreMark data
9.4 Electrical pin characteristics
External signal generator providing 1 MHz to 20 MHz signal drives the XTALIN input; when testing
1 MHz to 19 MHz the system PLL is OFF, SYSAHBCLKDIV = 1; when testing 20 MHz to 50 MHz
the system PLL is configured so that SYSAHBCLKDIV = 1.
Fig 10. CoreMark current consumption for power modes 0, 1, 2, and 3
002aah163
0 10 20 30 40 50
0
2.8
5.6
8.4
11.2
14
frequency (MHz)
I
DD
(mA)
mode 0
mode 1
mode 2
mode 3
Conditions: V
DD
= 3.3 V; standard port pins.
Fig 11. Typical LOW-level output current I
OL
versus LOW-level output voltage V
OL
V
OL
(V)
0 0.60.40.2
002aae991
5
10
15
I
OL
(mA)
0
T = 85 °C
25 °C
−40 °C