Datasheet

LPC1102_1104 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 7 — 26 September 2013 32 of 43
NXP Semiconductors
LPC1102/1104
32-bit ARM Cortex-M0 microcontroller
10.5 I/O pins
[1] Applies to standard port pins and RESET pin.
10.6 SPI interfaces
[1] T
cy(clk)
= (SSPCLKDIV  (1 + SCR)  CPSDVSR) / f
main
. The clock cycle time derived from the SPI bit rate T
cy(clk)
is a function of the
main clock frequency f
main
, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register),
and the SPI CPSDVSR parameter (specified in the SPI clock prescale register).
[2] T
amb
= 40 C to 85 C.
[3] T
cy(clk)
= 12  T
cy(PCLK)
.
[4] T
amb
= 25 C; for normal voltage supply range: V
DD
= 3.3 V.
Table 13. Dynamic characteristic: I/O pins
[1]
T
amb
=  40  C to +85  C; 3.0 V  V
DD
 3.6 V.
Symbol Parameter Conditions Min Typ Max Unit
t
r
rise time pin
configured as
output
3.0 - 5.0 ns
t
f
fall time pin
configured as
output
2.5 - 5.0 ns
Table 14. Dynamic characteristics of SPI pins in SPI mode
Symbol Parameter Conditions Min Typ Max Unit
SPI master (in SPI mode)
T
cy(clk)
clock cycle time when only receiving
[1]
50 - - ns
when only transmitting
[1]
40 ns
t
DS
data set-up time in SPI mode
2.4 V  V
DD
 3.6 V
[2]
15 - - ns
2.0 V  V
DD
< 2.4 V
[2]
20 ns
1.8 V  V
DD
< 2.0 V
[2]
24 - - ns
t
DH
data hold time in SPI mode
[2]
0-- ns
t
v(Q)
data output valid time in SPI mode
[2]
--10 ns
t
h(Q)
data output hold time in SPI mode
[2]
0-- ns
SPI slave (in SPI mode)
T
cy(PCLK)
PCLK cycle time 20 - - ns
t
DS
data set-up time in SPI mode
[3][4]
0-- ns
t
DH
data hold time in SPI mode
[3][4]
3  T
cy(PCLK)
+ 4 - - ns
t
v(Q)
data output valid time in SPI mode
[3][4]
--3  T
cy(PCLK)
+ 11 ns
t
h(Q)
data output hold time in SPI mode
[3][4]
--2  T
cy(PCLK)
+ 5 ns