Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 197 of 547
13.1 How to read this chapter
The UART block is identical for all LPC111x, LPC11D14, and LPC11Cxx parts. The DSR,
DCD
, and RI modem signals are fully pinned out on the LQFP48 packages only.
Note that for parts of the LPC1100 series (LPC111x/101/201/301), the UART pins must be
configured before the UART clock can be enabled. No enabling sequence requirement
exists for parts LPC11Cxx , parts in the LPC1100L and LPC1100XL series, and
LPC11D14.
13.2 Basic configuration
The UART is configured using the following registers:
1. Pins: For the LPC111x/101/201/301 parts, the UART pins must be configured in the
IOCONFIG register block (Section 7.4
) before the UART clocks can be enabled in the
SYSAHBCLKCTRL register. For all other parts, no special enabling sequence is
required.
Remark: If the modem input pins are used, the modem function location must be also
selected in the UART location registers (Section 7.4
)
2. Power: In the SYSAHBCLKCTRL register, set bit 12 (Table 21
).
3. Peripheral clock: Enable the UART peripheral clock by writing to the UARTCLKDIV
register (Table 23
).
13.3 Features
• 16-byte receive and transmit FIFOs.
• Register locations conform to ‘550 industry standard.
• Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.
• Built-in baud rate generator.
• UART allows for implementation of either software or hardware flow control.
• RS-485/EIA-485 9-bit mode support with output enable.
• Modem control.
UM10398
Chapter 13: LPC111x/LPC11Cxx UART
Rev. 12.3 — 10 June 2014 User manual