Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 209 of 547
NXP Semiconductors
UM10398
Chapter 13: LPC111x/LPC11Cxx UART
While starting transmission of the initial character, the CTS signal is asserted.
Transmission will stall as soon as the pending transmission has completed. The UART will
continue transmitting a 1 bit as long as CTS
is de-asserted (high). As soon as CTS gets
de-asserted, transmission resumes and a start bit is sent followed by the data bits of the
next character.
13.5.9 UART Line Status Register (U0LSR - 0x4000 8014, Read Only)
The U0LSR is a Read Only register that provides status information on the UART TX and
RX blocks.
Fig 33. Auto-CTS Functional Timing
start bits0..7 start bits0..7 stop start bits0..7 stop
UART1 TX
CTS1 pin
~ ~
~ ~
~ ~
~ ~
stop
Table 196. UART Line Status Register (U0LSR - address 0x4000 8014, Read Only) bit
description
Bit Symbol Value Description Reset
Value
0 RDR Receiver Data Ready. U0LSR[0] is set when the U0RBR holds
an unread character and is cleared when the UART RBR FIFO
is empty.
0
0 U0RBR is empty.
1 U0RBR contains valid data.
1 OE Overrun Error. The overrun error condition is set as soon as it
occurs. A U0LSR read clears U0LSR[1]. U0LSR[1] is set when
UART RSR has a new character assembled and the UART
RBR FIFO is full. In this case, the UART RBR FIFO will not be
overwritten and the character in the UART RSR will be lost.
0
0 Overrun error status is inactive.
1 Overrun error status is active.
2 PE Parity Error. When the parity bit of a received character is in
the wrong state, a parity error occurs. A U0LSR read clears
U0LSR[2]. Time of parity error detection is dependent on
U0FCR[0].
Note: A parity error is associated with the character at the top
of the UART RBR FIFO.
0
0 Parity error status is inactive.
1 Parity error status is active.