Datasheet
UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 304 of 547
NXP Semiconductors
UM10398
Chapter 16: LPC111x/LPC11Cxx C_CAN controller
16.6.3.8 CAN message valid 2 register
This register contains the MSGVAL bits of message objects 32 to 17. By reading out the
MSGVAL bits, the CPU can check which Message Object is valid. The MSGVAL bit of a
specific Message Object can be set/reset by the CPU via the IFx Message Interface
Registers.
16.6.4 CAN timing register
16.6.4.1 CAN clock divider register
This register determines the CAN clock signal. The CAN_CLK is derived from the
peripheral clock PCLK divided by the values in this register.
16.7 Functional description
16.7.1 C_CAN controller state after reset
After a hardware reset, the registers hold the values described in Table 245. Additionally,
the busoff state is reset and the output CAN_TXD is set to recessive (HIGH). The value
0x0001 (INIT = ‘1’) in the CAN Control Register enables the software initialization. The
CAN controller does not communicate with the CAN bus until the CPU resets INIT to ‘0’.
The data stored in the message RAM is not affected by a hardware reset. After power-on,
the contents of the message RAM is undefined.
Table 274. CAN message valid 2 register (CANMSGV2, address 0x4005 0164) bit description
Bit Symbol Description Access Reset
value
15:0 MSGVAL32_17 Message valid bits of message objects 32 to 17.
0 = This message object is ignored by the message
handler.
1 = This message object is configured and should
be considered by the message handler.
R 0x00
31:16 - Reserved - -
Table 275. CAN clock divider register (CANCLKDIV, address 0x4005 0180) bit description
Bit Symbol Description Reset
value
Access
3:0 CLKDIVVAL Clock divider value. CAN_CLK =
PCLK/(CLKDIVVAL +1)
0000: CAN_CLK = PCLK divided by 1.
0001: CAN_CLK = PCLK divided by 2.
0010: CAN_CLK = PCLK divided by 3
0011: CAN_CLK = PCLK divided by 4.
...
1111: CAN_CLK = PCLK divided by 16.
1R/W
31:4 - reserved - -