Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 32 of 547
NXP Semiconductors
UM10398
Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)
3.5.13 System AHB clock divider register
This register divides the main clock to provide the system clock to the core, memories,
and the peripherals. The system clock can be shut down completely by setting the DIV
bits to 0x0.
3.5.14 System AHB clock control register
The AHBCLKCTRL register enables the clocks to individual system and peripheral blocks.
The system clock (sys_ahb_clk[0], bit 0 in the AHBCLKCTRL register) provides the clock
for the AHB to APB bridge, the AHB matrix, the ARM Cortex-M0, the Syscon block, and
the PMU. This clock cannot be disabled.
Table 19. Main clock source update enable register (MAINCLKUEN, address 0x4004 8074)
bit description
Bit Symbol Value Description Reset value
0 ENA Enable main clock source update 0x0
0 No change
1 Update clock source
31:1 - - Reserved 0x00
Table 20. System AHB clock divider register (SYSAHBCLKDIV, address 0x4004 8078) bit
description
Bit Symbol Description Reset value
7:0 DIV System AHB clock divider values
0: System clock disabled.
1: Divide by 1.
to
255: Divide by 255.
0x01
31:8 - Reserved 0x00
Table 21. System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit
description
Bit Symbol Value Description Reset
value
0 SYS Enables clock for AHB to APB bridge, to the AHB
matrix, to the Cortex-M0 FCLK and HCLK, to the
SysCon, and to the PMU. This bit is read only.
1
0 Reserved
1 Enable
1 ROM Enables clock for ROM. 1
0 Disable
1 Enable
2 RAM Enables clock for RAM. 1
0 Disable
1 Enable
3 FLASHREG Enables clock for flash register interface. 1
0 Disabled
1 Enabled