Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 358 of 547
NXP Semiconductors
UM10398
Chapter 19: LPC1100XL series: 16-bit counter/timer CT16B0/1
19.7.12 PWM Control register (TMR16B0PWMC and TMR16B1PWMC)
The PWM Control Register is used to configure the match outputs as PWM outputs. Each
match output can be independently set to perform either as PWM output or as match
output whose function is controlled by the External Match Register (EMR).
For timer 0, three single-edge controlled PWM outputs can be selected on the
CT16B0_MAT[2:0] outputs. For timer 1, two single-edged PWM outputs can be selected
on the CT16B1_Mat[1:0] outputs. One additional match register determines the PWM
cycle length. When a match occurs in any of the other match registers, the PWM output is
set to HIGH. The timer is reset by the match register that is configured to set the PWM
cycle length. When the timer is reset to zero, all currently HIGH match outputs configured
as PWM outputs are cleared.
7:5 SELCC When bit 4 is one, these bits select which capture input edge
will cause the timer and prescaler to be cleared. These bits
have no effect when bit 4 is zero.
0
0x0 Rising Edge of CAP0 clears the timer (if bit 4 is set).
0x1 Falling Edge of CAP0 clears the timer (if bit 4 is set).
0x2 Rising Edge of CAP1 clears the timer (if bit 4 is set).
0x3 Falling Edge of CAP1 clears the timer (if bit 4 is set).
0x4 Reserved.
0x5 Reserved.
0x6 Reserved.
0x7 Reserved.
31:8 - - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
-
Table 309. Count Control Register (TMR16B0CTCR - address 0x4000 C070 and
TMR16B1CTCR - address 0x4001 0070) bit description
Bit Symbol Value Description Reset
value
Table 310. PWM Control Register (TMR16B0PWMC - address 0x4000 C074 and
TMR16B1PWMC- address 0x4001 0074) bit description
Bit Symbol Value Description Reset
value
0 PWMEN0 PWM channel0 enable 0
0 CT16Bn_MAT0 is controlled by EM0.
1 PWM mode is enabled for CT16Bn_MAT0.
1 PWMEN1 PWM channel1 enable 0
0 CT16Bn_MAT1 is controlled by EM1.
1 PWM mode is enabled for CT16Bn_MAT1.
2 PWMEN2 PWM channel2 enable 0
0 Match channel 2 or pin CT16B0_MAT2 is controlled by
EM2. Match channel 2 is not pinned out on timer 1.
1 PWM mode is enabled for match channel 2 or pin
CT16B0_MAT2.