Datasheet
UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 359 of 547
NXP Semiconductors
UM10398
Chapter 19: LPC1100XL series: 16-bit counter/timer CT16B0/1
19.7.13 Rules for single edge controlled PWM outputs
1. All single edge controlled PWM outputs go LOW at the beginning of each PWM cycle
(timer is set to zero) unless their match value is equal to zero.
2. Each PWM output will go HIGH when its match value is reached. If no match occurs
(i.e. the match value is greater than the PWM cycle length), the PWM output remains
continuously LOW.
3. If a match value larger than the PWM cycle length is written to the match register, and
the PWM signal is HIGH already, then the PWM signal will be cleared on the next start
of the next PWM cycle.
4. If a match register contains the same value as the timer reset value (the PWM cycle
length), then the PWM output will be reset to LOW on the next clock tick. Therefore,
the PWM output will always consist of a one clock tick wide positive pulse with a
period determined by the PWM cycle length (i.e. the timer reload value).
5. If a match register is set to zero, then the PWM output will go to HIGH the first time the
timer goes back to zero and will stay HIGH continuously.
Note: When the match outputs are selected to serve as PWM outputs, the timer reset
(MRnR) and timer stop (MRnS) bits in the Match Control Register MCR must be set to 0
except for the match register setting the PWM cycle length. For this register, set the
MRnR bit to 1 to enable the timer reset when the timer value matches the value of the
corresponding match register.
3 PWMEN3 PWM channel3 enable
Note: It is recommended to use match channel 3 to set
the PWM cycle because it is not pinned out.
0
0 Match channel 3 match channel 3 is controlled by EM3.
1 PWM mode is enabled for match channel 3match
channel 3.
31:4 - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
NA
Table 310. PWM Control Register (TMR16B0PWMC - address 0x4000 C074 and
TMR16B1PWMC- address 0x4001 0074) bit description
Bit Symbol Value Description Reset
value
Fig 73. Sample PWM waveforms with a PWM cycle length of 100 (selected by MR2) and
MAT2:0 enabled as PWM outputs by the PWCM register.
100
(counter is reset)
04165
PWM0/MAT0
PWM1/MAT1
PWM2/MAT2 MR2 = 100
MR1 = 41
MR0 = 65