Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 376 of 547
21.1 How to read this chapter
The 32-bit timer blocks are identical for all LPC1100XL parts.
Compared to the timer block for the LPC1100/LPC1100L/LPC1100C series, the following
features have been added:
One additional capture input for each timer.
Capture-clear function for easy pulse-width measurement (see Section 21.7.11).
21.2 Basic configuration
The CT32B0/1 are configured using the following registers:
1. Pins: The CT32B0/1 pins must be configured in the IOCONFIG register block
(Section 7.4
).
2. Power and peripheral clock: In the SYSAHBCLKCTRL register, set bit 9 and bit 10
(Table 21
). The peripheral clock (PCLK) is provided by the system clock (see
Table 20
).
21.3 Features
Two 32-bit counter/timers with a programmable 32-bit prescaler.
Counter or Timer operation.
The timer and prescaler may be configured to be cleared on a designated capture
event. This feature permits easy pulse-width measurement by clearing the timer on
the leading edge of an input pulse and capturing the timer value on the trailing edge.
Two 32-bit capture channels that can take a snapshot of the timer value when an input
signal transitions. A capture event may also optionally generate an interrupt.
Four 32-bit match registers that allow:
Continuous operation with optional interrupt generation on match.
Stop timer on match with optional interrupt generation.
Reset timer on match with optional interrupt generation.
Up to four external outputs corresponding to match registers with the following
capabilities:
Set LOW on match.
Set HIGH on match.
Toggle on match.
Do nothing on match.
For each timer, up to four match registers can be configured as PWM allowing to use
up to three match outputs as single edge controlled PWM outputs.
UM10398
Chapter 21: LPC1100XL series: 32-bit counter/timer CT32B0/1
Rev. 12.3 — 10 June 2014 User manual