Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 467 of 547
NXP Semiconductors
UM10398
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
[1] To simplify the software layer, the CMSIS only uses IRQ numbers and therefore uses negative values for
exceptions other than interrupts. The IPSR returns the Exception number, see Table 28–423
.
[2] See Section 28.4.3.4
for more information.
[3] See Section 28–28.6.2.6
.
[4] Increasing in steps of 4.
For an asynchronous exception, other than reset, the processor can execute additional
instructions between when the exception is triggered and when the processor enters the
exception handler.
Privileged software can disable the exceptions that Table 28–428
shows as having
configurable priority, see Section 28–28.6.2.3
.
For more information about HardFaults, see Section 28–28.4.4
.
28.4.3.3 Exception handlers
The processor handles exceptions using:
Interrupt Service Routines (ISRs) — Interrupts IRQ0 to IRQ31 are the exceptions
handled by ISRs.
Fault handler — HardFault is the only exception handled by the fault handler.
System handlers — NMI, PendSV, SVCall SysTick, and HardFault are all system
exceptions handled by system handlers.
28.4.3.4 Vector table
The vector table contains the reset value of the stack pointer, and the start addresses,
also called exception vectors, for all exception handlers. Figure 28–101
shows the order
of the exception vectors in the vector table. The least-significant bit of each vector must be
1, indicating that the exception handler is written in Thumb code.
12-13 - Reserved - -
14 -2 PendSV Configurable
[3]
0x00000038
15 -1 SysTick Configurable
[3]
0x0000003C
16 and above 0 and above Interrupt (IRQ) Configurable
[3]
0x00000040 and
above
[4]
Table 428. Properties of different exception types
Exception
number
[1]
IRQ
number
[1]
Exception
type
Priority Vector
address
[2]