Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 501 of 547
NXP Semiconductors
UM10398
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
28.5.7.4.4 Condition flags
This instruction does not change the flags.
28.5.7.4.5 Examples
DSB ; Data Synchronisation Barrier
28.5.7.5 ISB
Instruction Synchronization Barrier.
28.5.7.5.1 Syntax
ISB
28.5.7.5.2 Operation
ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor,
so that all instructions following the ISB are fetched from cache or memory again, after the
ISB instruction has been completed.
28.5.7.5.3 Restrictions
There are no restrictions.
28.5.7.5.4 Condition flags
This instruction does not change the flags.
28.5.7.5.5 Examples
ISB ; Instruction Synchronisation Barrier
28.5.7.6 MRS
Move the contents of a special register to a general-purpose register.
28.5.7.6.1 Syntax
MRS Rd, spec_reg
where:
Rd is the general-purpose destination register.
spec_reg is one of the special-purpose registers: APSR, IPSR, EPSR, IEPSR, IAPSR,
EAPSR, PSR, MSP, PSP, PRIMASK, or CONTROL.
28.5.7.6.2 Operation
MRS stores the contents of a special-purpose register to a general-purpose register. The
MRS instruction can be combined with the MR instruction to produce read-modify-write
sequences, which are suitable for modifying a specific flag in the PSR.
See Section 28–28.5.7.7
.
28.5.7.6.3 Restrictions
In this instruction, Rd must not be SP or PC.