Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 530 of 547
NXP Semiconductors
UM10398
Chapter 29: Supplementary information
addresses 0x4001 0018 to 24) bit description 354
Table 305. Capture Control Register (TMR16B0CCR -
address 0x4000 C028 and TMR16B1CCR -
address 0x4001 0028) bit description. . . . . . .354
Table 306: Capture registers (TMR16B0CR0/1, address
0x4000 C02C/30 and TMR16B1CR0/1, address
0x4001 002C/30) bit description. . . . . . . . . . .355
Table 307. External Match Register (TMR16B0EMR -
address 0x4000 C03C and TMR16B1EMR -
address 0x4001 003C) bit description . . . . . .355
Table 308. External match control. . . . . . . . . . . . . . . . . .356
Table 309. Count Control Register (TMR16B0CTCR -
address 0x4000 C070 and TMR16B1CTCR -
address 0x4001 0070) bit description. . . . . . .357
Table 310. PWM Control Register (TMR16B0PWMC -
address 0x4000 C074 and TMR16B1PWMC-
address 0x4001 0074) bit description. . . . . . .358
Table 311. Counter/timer pin description . . . . . . . . . . . . .363
Table 312. Register overview: 32-bit counter/timer 0 CT32B0
(base address 0x4001 4000) . . . . . . . . . . . .363
Table 313. Register overview: 32-bit counter/timer 1 CT32B1
(base address 0x4001 8000) . . . . . . . . . . . .364
Table 314: Interrupt Register (TMR32B0IR - address
0x4001 4000 and TMR32B1IR - address
0x4001 8000) bit description . . . . . . . . . . . . .365
Table 315: Timer Control Register (TMR32B0TCR - address
0x4001 4004 and TMR32B1TCR - address
0x4001 8004) bit description . . . . . . . . . . . . .366
Table 316: Timer counter registers (TMR32B0TC, address
0x4001 4008 and TMR32B1TC 0x4001 8008) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .366
Table 317: Prescale registers (TMR32B0PR, address
0x4001 400C and TMR32B1PR 0x4001 800C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .366
Table 318: Prescale counter registers (TMR32B0PC,
address 0x4001 4010 and TMR32B1PC
0x4001 8010) bit description . . . . . . . . . . . . .367
Table 319: Match Control Register (TMR32B0MCR -
address 0x4001 4014 and TMR32B1MCR -
address 0x4001 8014) bit description. . . . . . .367
Table 320: Match registers (TMR32B0MR0 to 3, addresses
0x4001 4018 to 24 and TMR32B1MR0 to 3,
addresses 0x4001 8018 to 24) bit description 368
Table 321: Capture Control Register (TMR32B0CCR -
address 0x4001 4028 and TMR32B1CCR -
address 0x4001 8028) bit description. . . . . . .368
Table 322: Capture registers (TMR32B0CR0, addresses
0x4001 402C and TMR32B1CR0, addresses
0x4001 802C) bit description . . . . . . . . . . . . .369
Table 323: External Match Register (TMR32B0EMR -
address 0x4001 403C and TMR32B1EMR -
address0x4001 803C) bit description . . . . . . .370
Table 324. External match control. . . . . . . . . . . . . . . . . .371
Table 325: Count Control Register (TMR32B0CTCR -
address 0x4001 4070 and TMR32B1TCR -
address 0x4001 8070) bit description . . . . . .372
Table 326: PWM Control Register (TMR32B0PWMC -
0x4001 4074 and TMR32B1PWMC - 0x4001
8074) bit description. . . . . . . . . . . . . . . . . . . . 372
Table 327. Counter/timer pin description . . . . . . . . . . . . 377
Table 328. Register overview: 32-bit counter/timer 0 CT32B0
(base address 0x4001 4000) . . . . . . . . . . . . 378
Table 329. Register overview: 32-bit counter/timer 1 CT32B1
(base address 0x4001 8000) . . . . . . . . . . . . 379
Table 330: Interrupt Register (TMR32B0IR - address
0x4001 4000 and TMR32B1IR - address
0x4001 8000) bit description . . . . . . . . . . . . . 380
Table 331: Timer Control Register (TMR32B0TCR - address
0x4001 4004 and TMR32B1TCR - address
0x4001 8004) bit description . . . . . . . . . . . . . 380
Table 332: Timer counter registers (TMR32B0TC, address
0x4001 4008 and TMR32B1TC 0x4001 8008) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
Table 333: Prescale registers (TMR32B0PR, address
0x4001 400C and TMR32B1PR 0x4001 800C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
Table 334: Prescale counter registers (TMR32B0PC,
address 0x4001 4010 and TMR32B1PC
0x4001 8010) bit description . . . . . . . . . . . . . 381
Table 335: Match Control Register (TMR32B0MCR -
address 0x4001 4014 and TMR32B1MCR -
address 0x4001 8014) bit description . . . . . . 381
Table 336: Match registers (TMR32B0MR0 to 3, addresses
0x4001 4018 to 24 and TMR32B1MR0 to 3,
addresses 0x4001 8018 to 24) bit description 383
Table 337: Capture Control Register (TMR32B0CCR -
address 0x4001 4028 and TMR32B1CCR -
address 0x4001 8028) bit description . . . . . . 383
Table 338: Capture registers (TMR32B0CR0/1, addresses
0x4001 402C/30 and TMR32B1CR0/1, addresses
0x4001 802C/30) bit description . . . . . . . . . . 384
Table 339: External Match Register (TMR32B0EMR -
address 0x4001 403C and TMR32B1EMR -
address0x4001 803C) bit description . . . . . . 384
Table 340. External match control . . . . . . . . . . . . . . . . . 385
Table 341: Count Control Register (TMR32B0CTCR -
address 0x4001 4070 and TMR32B1TCR -
address 0x4001 8070) bit description . . . . . 386
Table 342: PWM Control Register (TMR32B0PWMC -
0x4001 4074 and TMR32B1PWMC - 0x4001
8074) bit description. . . . . . . . . . . . . . . . . . . . 387
Table 343. Register overview: Watchdog timer (base
address 0x4000 4000) . . . . . . . . . . . . . . . . . . 394
Table 344: Watchdog Mode register (WDMOD -
0
x4000 4000) bit description . . . . . . . . . . . . . 394
Table 345. Watchdog operating modes selection . . . . . . 395
Table 346: Watchdog Timer Constant register (WDTC -
0x4000 4004) bit description . . . . . . . . . . . . . 396
Table 347: Watchdog Feed register (WDFEED -
0x4000 4008) bit description . . . . . . . . . . . . . 396
Table 348: Watchdog Timer Value register (WDTV -
0x4000 400C) bit description . . . . . . . . . . . . . 396
Table 349: Watchdog Timer Warning Interrupt register
(WDWARNINT - 0x4000 4014) bit description397
Table 350: Watchdog Timer Window register (WDWINDOW
- 0x4000 4018) bit description . . . . . . . . . . . . 397