Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller HVQFN 32 (7x7) 32-Bit 50 MHz I/O number 28

531

532

533

534

535

536

537

538

539

540

User manual Rev. 12.3 — 10 June 2014 533 of 547

NXP Semiconductors

UM10398

Chapter 29: Supplementary information

29.5 Figures

Fig 1. LPC111x block diagram (LPC1100 and LPC1100L

series) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Fig 2. LPC111x block diagram (LPC1100XL series) . . .15

Fig 3. LPC11Cxx/LPC11D14 block diagram (LPC1100C

series and LPC11D14). . . . . . . . . . . . . . . . . . . . .16

Fig 4. LPC11D14 block diagram . . . . . . . . . . . . . . . . . .17

Fig 5. PCF8576D block diagram . . . . . . . . . . . . . . . . . .17

Fig 6. LPC111x/LPC11Cxx memory map (LPC1100 and

LPC1100L series) . . . . . . . . . . . . . . . . . . . . . . . .20

Fig 7. LPC111x memory map (LPC1100XL series) . . . .21

Fig 8. LPC111x/LPC11Cxx CGU block diagram . . . . . .24

Fig 9. Start-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Fig 10. System PLL block diagram . . . . . . . . . . . . . . . . .53

Fig 11. Power profiles pointer structure . . . . . . . . . . . . . .61

Fig 12. LPC111x/102/202/302 clock configuration for power

API use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Fig 13. Power profiles usage . . . . . . . . . . . . . . . . . . . . . .66

Fig 14. Standard I/O pin configuration . . . . . . . . . . . . . . .72

Fig 15. Standard I/O pin configuration . . . . . . . . . . . . . .106

Fig 16. Pin configuration LQFP48 package . . . . . . . . . .143

Fig 17. Pin configuration HVQFN33 package . . . . . . . .144

Fig 18. Pin configuration HVQFN24 package . . . . . . . .144

Fig 19. Pin configuration LQFP48 package . . . . . . . . . .145

Fig 20. Pin configuration (LPC11C22/C24) . . . . . . . . . .146

Fig 21. Pin configuration LQFP100 package . . . . . . . . .147

Fig 22. Pin configuration SO20 package . . . . . . . . . . . .167

Fig 23. Pin configuration TSSOP20 package with I

C-bus

pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168

Fig 24. Pin configuration TSSOP20 package with V

DDA

and

SSA

pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170

Fig 25. Pin configuration TSSOP28 package . . . . . . . .173

Fig 26. Pin configuration DIP28 package. . . . . . . . . . . .173

Fig 27. Pin configuration LQFP48 package . . . . . . . . . .178

Fig 28. LPC1100XL series pin configuration TFBGA48

package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179

Fig 29. Pin configuration HVQFN33 package . . . . . . . .180

Fig 30. Masked write operation to the GPIODATA

Fig 31. Masked read operation . . . . . . . . . . . . . . . . . . .196

Fig 32. Auto-RTS Functional Timing . . . . . . . . . . . . . . .208

Fig 33. Auto-CTS Functional Timing . . . . . . . . . . . . . . .209

Fig 34. Auto-baud a) mode 0 and b) mode 1 waveform 214

Fig 35. Algorithm for setting UART dividers. . . . . . . . . .217

Fig 36. UART block diagram . . . . . . . . . . . . . . . . . . . . .223

Fig 37. Texas Instruments Synchronous Serial Frame

Format: a) Single and b) Continuous/back-to-back

Two Frames Transfer. . . . . . . . . . . . . . . . . . . . .232

Fig 38. SPI frame format with CPOL=0 and CPHA=0 (a)

Single and b) Continuous Transfer). . . . . . . . . .233

Fig 39. SPI frame format with CPOL=0 and CPHA=1 . .234

Fig 40. SPI frame format with CPOL = 1 and CPHA = 0 (a)

Single and b) Continuous Transfer). . . . . . . . . .235

Fig 41. SPI Frame Format with CPOL = 1 and

CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236

Fig 42. Microwire frame format (single transfer) . . . . . .237

Fig 43. Microwire frame format (continuous transfers) .237

Fig 44. Microwire frame format setup and hold details . 238

Fig 45. I

C-bus configuration. . . . . . . . . . . . . . . . . . . . . 240

Fig 46. Format in the Master Transmitter mode . . . . . . 250

Fig 47. Format of Master Receiver mode . . . . . . . . . . . 251

Fig 48. A Master Receiver switches to Master Transmitter

after sending Repeated START . . . . . . . . . . . . 251

Fig 49. Format of Slave Receiver mode . . . . . . . . . . . . 252

Fig 50. Format of Slave Transmitter mode . . . . . . . . . . 252

Fig 51. I

C serial interface block diagram . . . . . . . . . . . 253

Fig 52. Arbitration procedure. . . . . . . . . . . . . . . . . . . . . 255

Fig 53. Serial clock synchronization . . . . . . . . . . . . . . . 255

Fig 54. Format and states in the Master Transmitter

mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

Fig 55. Format and states in the Master Receiver

mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

Fig 56. Format and states in the Slave Receiver mode 267

Fig 57. Format and states in the Slave Transmitter

mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

Fig 58. Simultaneous Repeated START conditions from two

masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

Fig 59. Forced access to a busy I

C-bus . . . . . . . . . . . 272

Fig 60. Recovering from a bus obstruction caused by a

LOW level on SDA . . . . . . . . . . . . . . . . . . . . . . 273

Fig 61. C_CAN block diagram. . . . . . . . . . . . . . . . . . . . 283

Fig 62. CAN core in Silent mode. . . . . . . . . . . . . . . . . . 307

Fig 63. CAN core in Loop-back mode . . . . . . . . . . . . . . 307

Fig 64. CAN core in Loop-back mode combined with Silent

mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

Fig 65. Block diagram of a message object transfer . . 310

Fig 66. Reading a message from the FIFO buffer to the

message buffer . . . . . . . . . . . . . . . . . . . . . . . . . 316

Fig 67. Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

Fig 68. CAN API pointer structure. . . . . . . . . . . . . . . . . 321

Fig 69. Sample PWM waveforms with a PWM cycle length

of 100 (selected by MR2) and MAT2:0 enabled as

PWM outputs by the PWCM register. . . . . . . . . 345

Fig 70. A timer cycle in which PR=2, MRx=6, and both

interrupt and reset on match are enabled . . . . . 345

Fig 71. A timer cycle in which PR=2, MRx=6, and both

interrupt and stop on match are enabled . . . . . 345

Fig 72. 16-bit counter/timer block diagram . . . . . . . . . . 346

Fig 73. Sample PWM waveforms with a PWM cycle length

of 100 (selected by MR2) and MAT2:0 enabled as

PWM outputs by the PWCM register. . . . . . . . . 359

Fig 74. A timer cycle in which PR=2, MRx=6, and both

interrupt and reset on match are enabled . . . . . 360

Fig 75. A timer cycle in which PR=2, MRx=6, and both

interrupt and stop on match are enabled . . . . . 360

Fig 76. 16-bit counter/timer block diagram . . . . . . . . . . 361

Fig 77. Sample PWM waveforms with a PWM cycle length

of 100 (selected by MR2) and MAT2:0 enabled as

PWM outputs by the PWCM register. . . . . . . . . 374

Fig 78. A timer cycle in which PR=2, MRx=6, and both

interrupt and reset on match are enabled . . . . . 374

Fig 79. A timer cycle in which PR=2, MRx=6, and both

interrupt and stop on match are enabled . . . . . 374