Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller HVQFN 32 (7x7) 32-Bit 50 MHz I/O number 28

531

532

533

534

535

536

537

538

539

540

User manual Rev. 12.3 — 10 June 2014 534 of 547

NXP Semiconductors

UM10398

Chapter 29: Supplementary information

Fig 80. 32-bit counter/timer block diagram. . . . . . . . . . .375

Fig 81. A timer cycle in which PR=2, MRx=6, and both

interrupt and reset on match are enabled . . . . .388

Fig 82. A timer cycle in which PR=2, MRx=6, and both

interrupt and stop on match are enabled . . . . . .389

Fig 83. Sample PWM waveforms with a PWM cycle length

of 100 (selected by MR2) and MAT2:0 enabled as

PWM outputs by the PWMC register. . . . . . . . .389

Fig 84. 32-bit counter/timer block diagram. . . . . . . . . . .390

Fig 85. Windowed Watchdog Timer (WWDT) block

diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393

Fig 86. Early Watchdog Feed with Windowed Mode

Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397

Fig 87. Correct Watchdog Feed with Windowed Mode

Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .398

Fig 88. Watchdog Warning Interrupt . . . . . . . . . . . . . . .398

Fig 89. Watchdog block diagram . . . . . . . . . . . . . . . . . .403

Fig 90. System tick timer block diagram . . . . . . . . . . . .404

Fig 91. Boot process flowchart . . . . . . . . . . . . . . . . . . .418

Fig 92. IAP parameter passing . . . . . . . . . . . . . . . . . . .440

Fig 93. Algorithm for generating a 128-bit signature . . .450

Fig 94. Connecting the SWD pins to a standard SWD

connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .452

Fig 95. Cortex-M0 implementation. . . . . . . . . . . . . . . . .453

Fig 96. Processor core register set . . . . . . . . . . . . . . . .456

Fig 97. APSR, IPSR, EPSR register bit assignments . .457

Fig 98. Generic ARM Cortex-M0 memory map . . . . . . .462

Fig 99. Memory ordering restrictions . . . . . . . . . . . . . . .463

Fig 100. Little-endian format . . . . . . . . . . . . . . . . . . . . . .465

Fig 101. Vector table . . . . . . . . . . . . . . . . . . . . . . . . . . . .468

Fig 102. Exception entry stack contents . . . . . . . . . . . . .470

Fig 103. ASR #3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .477

Fig 104. LSR #3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .478

Fig 105. LSL #3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .478

Fig 106. ROR #3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .479

Fig 107. IPR register . . . . . . . . . . . . . . . . . . . . . . . . . . . .508