Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 75 of 547
NXP Semiconductors
UM10398
Chapter 7: LPC1100/LPC1100C/LPC1100L series: I/O configuration
IOCON_PIO0_5 R/W 0x034 I/O configuration for pin PIO0_5/SDA 0x00 Table 69
IOCON_PIO1_9 R/W 0x038 I/O configuration for pin
PIO1_9/CT16B1_MAT0
0xD0 Ta ble 70
IOCON_PIO3_4 R/W 0x03C I/O configuration for pin PIO3_4 0xD0 Table 71
IOCON_PIO2_4 R/W 0x040 I/O configuration for pin PIO2_4 0xD0 Table 72
IOCON_PIO2_5 R/W 0x044 I/O configuration for pin PIO2_5 0xD0 Table 73
IOCON_PIO3_5 R/W 0x048 I/O configuration for pin PIO3_5 0xD0 Table 74
IOCON_PIO0_6 R/W 0x04C I/O configuration for pin PIO0_6/SCK0 0xD0 Ta ble 75
IOCON_PIO0_7 R/W 0x050 I/O configuration for pin PIO0_7/CTS 0xD0 Table 76
IOCON_PIO2_9 R/W 0x054 I/O configuration for pin PIO2_9 0xD0 Table 77
IOCON_PIO2_10 R/W 0x058 I/O configuration for pin PIO2_10 0xD0 Table 78
IOCON_PIO2_2 R/W 0x05C I/O configuration for pin
PIO2_2/DCD/MISO1
0xD0 Ta ble 79
IOCON_PIO0_8 R/W 0x060 I/O configuration for pin
PIO0_8/MISO0/CT16B0_MAT0
0xD0 Ta ble 80
IOCON_PIO0_9 R/W 0x064 I/O configuration for pin
PIO0_9/MOSI0/CT16B0_MAT1
0xD0 Ta ble 81
IOCON_SWCLK_PIO0_10 R/W 0x068 I/O configuration for pin
SWCLK/PIO0_10/
SCK0/CT16B0_MAT2
0xD0 Ta ble 82
IOCON_PIO1_10 R/W 0x06C I/O configuration for pin
PIO1_10/AD6/CT16B1_MAT1
0xD0 Ta ble 83
IOCON_PIO2_11 R/W 0x070 I/O configuration for pin PIO2_11/SCK0 0xD0 Table 84
IOCON_R_PIO0_11 R/W 0x074 I/O configuration for pin
R/PIO0_11/AD0/CT32B0_MAT3
0xD0 Ta ble 85
IOCON_R_PIO1_0 R/W 0x078 I/O configuration for pin
R/PIO1_0/AD1/CT32B1_CAP0
0xD0 Ta ble 86
IOCON_R_PIO1_1 R/W 0x07C I/O configuration for pin
R/PIO1_1/AD2/CT32B1_MAT0
0xD0 Ta ble 87
IOCON_R_PIO1_2 R/W 0x080 I/O configuration for pin
R/PIO1_2/AD3/CT32B1_MAT1
0xD0 Ta ble 88
IOCON_PIO3_0 R/W 0x084 I/O configuration for pin PIO3_0/DTR 0xD0 Table 89
IOCON_PIO3_1 R/W 0x088 I/O configuration for pin PIO3_1/DSR 0xD0 Table 90
IOCON_PIO2_3 R/W 0x08C I/O configuration for pin
PIO2_3/RI
/MOSI1
0xD0 Ta ble 91
IOCON_SWDIO_PIO1_3 R/W 0x090 I/O configuration for pin
SWDIO/PIO1_3/AD4/CT32B1_MAT2
0xD0 Ta ble 92
IOCON_PIO1_4 R/W 0x094 I/O configuration for pin
PIO1_4/AD5/CT32B1_MAT3
0xD0 Ta ble 93
IOCON_PIO1_11 R/W 0x098 I/O configuration for pin PIO1_11/AD7 0xD0 Table 94
IOCON_PIO3_2 R/W 0x09C I/O configuration for pin PIO3_2/DCD 0xD0 Table 95
IOCON_PIO1_5 R/W 0x0A0 I/O configuration for pin
PIO1_5/RTS
/CT32B0_CAP0
0xD0 Ta ble 96
Table 56. Register overview: I/O configuration (base address 0x4004 4000)
Name Access Address
offset
Description Reset
value
Reference