Datasheet

LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 17 of 127
NXP Semiconductors
LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Fig 9. LPC1100L series pin configuration TSSOP20 package with I
2
C-bus pins
LPC1111FDH20/002
PIO0_8/MISO0/CT16B0_MAT0 PIO0_4/SCL
PIO0_9/MOSI0/CT16B0_MAT1 PIO0_2/SSEL0/CT16B0_CAP0
SWCLK/PIO0_10/SCK0/CT16B0_MAT2 PIO0_1/CLKOUT/CT32B0_MAT2
R/PIO0_11/AD0/CT32B0_MAT3 RESET/PIO0_0
PIO0_5/SDA V
SS
PIO0_6/SCK0 V
DD
R/PIO1_0/AD1/CT32B1_CAP0 XTALIN
R/PIO1_1/AD2/CT32B1_MAT0 XTALOUT
R/PIO1_2/AD3/CT32B1_MAT1 PIO1_7/TXD/CT32B0_MAT1
SWDIO/PIO1_3/AD4/CT32B1_MAT2 PIO1_6/RXD/CT32B0_MAT0
002aag596
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
Fig 10. LPC1100L series pin configuration TSSOP20 package with V
DDA
and V
SSA
pins
LPC1112FDH20/102
PIO0_8/MISO0/CT16B0_MAT0 PIO0_3
PIO0_9/MOSI0/CT16B0_MAT1 PIO0_2/SSEL0/CT16B0_CAP0
SWCLK/PIO0_10/SCK0/CT16B0_MAT2 PIO0_1/CLKOUT/CT32B0_MAT2
R/PIO0_11/AD0/CT32B0_MAT3 RESET/PIO0_0
V
DDA
V
SS
V
SSA
V
DD
R/PIO1_0/AD1/CT32B1_CAP0 XTALIN
R/PIO1_1/AD2/CT32B1_MAT0 XTALOUT
R/PIO1_2/AD3/CT32B1_MAT1 PIO1_7/TXD/CT32B0_MAT1
SWDIO/PIO1_3/AD4/CT32B1_MAT2 PIO1_6/RXD/CT32B0_MAT0
002aag597
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
Fig 11. LPC1100L series pin configuration HVQFN24 package
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LPC1112FHN24
Transparent top view
PIO0_9
V
DD
PIO1_8
PIO0_10
XTALIN PIO0_11
V
SS
PIO1_0
PIO0_1 PIO1_1
RESET/PIO0_0 PIO1_2
PIO0_2 PIO0_4 PIO0_5 PIO0_6 PIO0_7 PIO0_8
PIO1_7 PIO1_6 V
DD
V
SS
PIO1_4 PIO1_3
terminal 1
index area
6
13
5
14
4 15
3 16
2 17
1
18
7 8 9
10 11 12
24 23 22 21 20 19