Datasheet

LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 21 of 127
NXP Semiconductors
LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full V
DD
level ); IA = inactive,
no pull-up/down enabled.
[2] 5 V tolerant pad. RESET
functionality is not available in Deep power-down mode.
[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 51
).
[4] I
2
C-bus pin compliant with the I
2
C-bus specification for I
2
C standard mode and I
2
C Fast-mode Plus. The pin requires an external pull-up
to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain
configuration applies to all functions on this pin.
[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 51
).
[6] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
Table 5. LPC1100L series: LPC1112 pin description table (TSSOP20 with V
DDA
and V
SSA
pins)
Symbol
Pin TSSOP20
Start
logic
input
Type Reset
state
[1]
Description
PIO0_0 to PIO0_11 I/O Port 0 — Port 0 is a 12-bit I/O port with individual direction
and function controls for each bit. The operation of port 0 pins
depends on the function selected through the IOCONFIG
register block.
RESET
/PIO0_0 17
[2]
yes I I; PU RESET — External reset input with 20 ns glitch filter. A
LOW-going pulse as short as 50 ns on this pin resets the
device, causing I/O ports and peripherals to take on their
default states, and processor execution to begin at address 0.
In deep power-down mode, this pin must be pulled HIGH
externally. The RESET
pin can be left unconnected or be
used as a GPIO pin if an external RESET function is not
needed and Deep power-down mode is not used.
I/O - PIO0_0 — General purpose digital input/output pin with 10 ns
glitch filter.
PIO0_1/CLKOUT/
CT32B0_MAT2
18
[3]
yes I/O I; PU PIO0_1 — General purpose digital input/output pin. A LOW
level on this pin during reset starts the ISP command handler.
O-CLKOUT — Clockout pin.
O-CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
PIO0_2/SSEL0/
CT16B0_CAP0
19
[3]
yes I/O I; PU PIO0_2 — General purpose digital input/output pin.
I/O - SSEL0 — Slave Select for SPI0.
I-CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
PIO0_3 20
[3]
yes I/O I; PU PIO0_3 — General purpose digital input/output pin.
PIO0_8/MISO0/
CT16B0_MAT0
1
[3]
yes I/O I; PU PIO0_8 — General purpose digital input/output pin.
I/O - MISO0 — Master In Slave Out for SPI0.
O-CT16B0_MAT0 — Match output 0 for 16-bit timer 0.
PIO0_9/MOSI0/
CT16B0_MAT1
2
[3]
yes I/O I; PU PIO0_9 — General purpose digital input/output pin.
I/O - MOSI0 — Master Out Slave In for SPI0.
O-CT16B0_MAT1 — Match output 1 for 16-bit timer 0.