Datasheet

LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 23 of 127
NXP Semiconductors
LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full V
DD
level ); IA = inactive,
no pull-up/down enabled.
[2] 5 V tolerant pad. RESET
functionality is not available in Deep power-down mode.
[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 51
).
[4] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 51
).
[5] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
V
DDA
5 - I - 3.3 V supply voltage to the ADC. Also used as the ADC
reference voltage.
XTALIN 14
[5]
- I - Input to the oscillator circuit and internal clock generator
circuits. Input voltage must not exceed 1.8 V.
XTALOUT 13
[5]
- O - Output from the oscillator amplifier.
V
SS
16 - I - Ground.
V
SSA
6 - I - Analog ground.
Table 5. LPC1100L series: LPC1112 pin description table (TSSOP20 with V
DDA
and V
SSA
pins) …continued
Symbol
Pin TSSOP20
Start
logic
input
Type Reset
state
[1]
Description
Table 6. LPC1100L series: LPC1112 (HVQFN24 package)
Symbol HVQFN
pin
Start
logic
input
Type Reset
state
[1]
Description
RESET
/PIO0_0 1
[2]
yes I I; PU RESET — External reset input with 20 ns glitch filter. A
LOW-going pulse as short as 50 ns on this pin resets the
device, causing I/O ports and peripherals to take on their
default states, and processor execution to begin at address 0.
In deep power-down mode, this pin must be pulled HIGH
externally. The RESET
pin can be left unconnected or be used
as a GPIO pin if an external RESET function is not needed and
Deep power-down mode is not used.
I/O - PIO0_0 — General purpose digital input/output pin with 10 ns
glitch filter.
PIO0_1/CLKOUT/
CT32B0_MAT2
2
[3]
yes I/O I; PU PIO0_1 — General purpose digital input/output pin. A LOW
level on this pin during reset starts the ISP command handler.
O-CLKOUT — Clockout pin.
O-CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
PIO0_2/SSEL0/
CT16B0_CAP0
7
[3]
yes I/O I; PU PIO0_2 — General purpose digital input/output pin.
I/O - SSEL0 — Slave Select for SPI0.
I-CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
PIO0_4/SCL 8
[4]
yes I/O I; IA PIO0_4 — General purpose digital input/output pin
(open-drain).
I/O - SCL — I
2
C-bus, open-drain clock input/output. High-current
sink only if I
2
C Fast-mode Plus is selected in the I/O
configuration register.