Datasheet

LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 50 of 127
NXP Semiconductors
LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
Master or slave operation
8-frame FIFOs for both transmit and receive
4-bit to 16-bit frame
7.10 I
2
C-bus serial I/O controller
The LPC1110/11/12/13/14/15 contain one I
2
C-bus controller.
Remark: Part LPC1112FDH20/102 does not contain the I
2
C-bus controller.
The I
2
C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line
(SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
2
C is a multi-master bus and can be
controlled by more than one bus master connected to it.
7.10.1 Features
The I
2
C-interface is a standard I
2
C-bus compliant interface with open-drain pins. The
I
2
C-bus interface also supports Fast-mode Plus with bit rates up to 1 Mbit/s.
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
2
C-bus can be used for test and diagnostic purposes.
The I
2
C-bus controller supports multiple address recognition and a bus monitor mode.
7.11 10-bit ADC
The LPC1110/11/12/13/14/15 contain one ADC. It is a single 10-bit successive
approximation ADC with eight channels.
7.11.1 Features
10-bit successive approximation ADC.
Input multiplexing among 8 pins.
Power-down mode.
Measurement range 0 V to V
DD
.
10-bit conversion time 2.44 s (up to 400 kSamples/s).
Burst conversion mode for single or multiple inputs.