Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 14 of 547
NXP Semiconductors
UM10398
Chapter 1: LPC111x/LPC11Cxx Introductory information
1.4 Block diagram
(1) LQFP48 packages only.
(2) Not on LPC1112FDH20/102.
(3) All pins available on LQFP48 and HVQFN33 packages. CT16B1_MAT1 not available on TSSOP28/DIP28 packages.
CT32B1_MAT3, CT16B1_CAP0, CT16B1_MAT[1:0], CT32B0_CAP0 not available on TSSOP20/SO20 packages.
CT16B1_MAT[1:0], CT32B0_CAP0 not available on the HVQFN24 package. XTALOUT not available on LPC1112FHN24.
(4) AD[7:0] available on LQFP48 and HVQFN33 packages. AD[5:0] available on TSSOP28/DIP28/HVQFN24packages. AD[4:0]
available on TSSOP20/SO20 packages.
(5) All pins available on LQFP48 packages. RXD, TXD, DTR
, CTS, RTS available on HVQFN 33 packages. RXD, TXD, CTS, RTS
available on TSSOP28/DIP28 packages. RXD, TXD available on TSSOP20/SO20 packages.
Fig 1. LPC111x block diagram (LPC1100 and LPC1100L series)
SRAM
1/2/4/8 kB
ARM
CORTEX-M0
TEST/DEBUG
INTERFACE
FLASH
4/8/16/24/32 kB
HIGH-SPEED
GPIO
AHB TO APB
BRIDGE
CLOCK
GENERATION,
POWER CONTROL,
SYSTEM
FUNCTIONS
XTALIN
XTALOUT
(3)
RESET
clocks and
controls
SWD
LPC1110/11/12/13/14
002aae696
slave
slave
slave slave
ROM
slave
AHB-LITE BUS
GPIO ports
PIO0/1/2/3
CLKOUT
IRC
POR
SPI0
10-bit ADC
UART
32-bit COUNTER/TIMER 0
I
2
C-BUS
(2)
WDT
IOCONFIG
CT32B0_MAT[3:0]
(3)
AD[7:0]
(4)
CT32B0_CAP0
(3)
SDA
SCL
RXD
TXD
DTR, DSR, CTS
(5)
,
DCD, RI, RTS
(5)
SYSTEM CONTROL
PMU
32-bit COUNTER/TIMER 1
CT32B1_MAT[3:0]
(3)
CT32B1_CAP0
(3)
16-bit COUNTER/TIMER 1
CT16B1_MAT[1:0]
(3)
CT16B1_CAP0
(3)
16-bit COUNTER/TIMER 0
CT16B0_MAT[2:0]
(3)
CT16B0_CAP0
(3)
SCK0, SSEL0
MISO0, MOSI
SCK1, SSEL1
MISO1, MOSI
SPI1
(1)
system bus