Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 199 of 547
NXP Semiconductors
UM10398
Chapter 13: LPC111x/LPC11Cxx UART
U0LCR R/W 0x00C Line Control Register. Contains controls for frame formatting and break
generation.
0x00
U0MCR R/W 0x010 Modem control register 0x00
U0LSR RO 0x014 Line Status Register. Contains flags for transmit and receive status,
including line errors.
0x60
U0MSR RO 0x018 Modem status register 0x00
U0SCR R/W 0x01C Scratch Pad Register. Eight-bit temporary storage for software. 0x00
U0ACR R/W 0x020 Auto-baud Control Register. Contains controls for the auto-baud feature. 0x00
- - 0x024 Reserved -
U0FDR R/W 0x028 Fractional Divider Register. Generates a clock input for the baud rate
divider.
0x10
- - 0x02C Reserved -
U0TER R/W 0x030 Transmit Enable Register. Turns off UART transmitter for use with software
flow control.
0x80
- - 0x034 -
0x048
Reserved -
U0RS485CTRL R/W 0x04C RS-485/EIA-485 Control. Contains controls to configure various aspects of
RS-485/EIA-485 modes.
0x00
U0RS485ADR
MATCH
R/W 0x050 RS-485/EIA-485 address match. Contains the address match value for
RS-485/EIA-485 mode.
0x00
U0RS485DLY R/W 0x054 RS-485/EIA-485 direction control delay. 0x00
Table 184. Register overview: UART (base address: 0x4000 8000)
Name Access Address
offset
Description Reset
value