Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 2 of 547
NXP Semiconductors
UM10398
LPC111x/LPC11Cxx User manual
Revision history
Rev Date Description
12.3 20140610 LPC111x/LPC11C1x/LPC11C2x User manual
Modifications: Section 5.2 added to describe the requirement to disable all interrupts before calling the power profiles and
the requirement to use default mode when calling the IAP functions.
12.2 20140324 LPC111x/LPC11C1x/LPC11C2x User manual
Modifications: • Parts LPC1112JHI33/203, LPC1114JHN33/333, LPC1115JET48/303, and LPC1115JBD48/303 added.
• C_CAN Figure 67 “Bit timing” and TSEG1 bit description in Table 249 “CAN bit timing register (CANBT,
address 0x4005 000C) bit description” updated for clarification.
• Section 16.7.5.2 “Calculating the C_CAN bit rate” added.
• Parts added: LPC1114JHI33/303, LPC1111JHN33/103, LPC1112JHN33/203, LPC1113JHN33/203,
LPC1114JHN33/303, LPC1114JBD48/333, LPC1112FHI33/102, LPC1114JBD48/303,
LPC1114JBD48/323, LPC1113JHN33/303, LPC1112JHN33/103, LPC1111JHN33/203,
LPC1114JHN33/203.
• Pin description tables for RESET/PIO0_0 updated: In deep power-down mode, this pin must be pulled
HIGH externally. The RESET pin can be left unconnected or be used as a GPIO pin if an external
RESET function is not needed.
• Pin description notes relating to open-drain I2C-bus pins updated for clarity.
• Pin description of the WAKEUP pin updated for clarity.
• Remark added to Section 3.9.3.3 “Wake-up from Deep-sleep mode”: After wake-up, reprogram the
clock source for the main clock.
12.1 20130807 LPC111x/LPC11C1x/LPC11C2x User manual
Modifications:
• Remove instruction breakpoints from feature list for SWD. See Section 27.2.
• IRQLATENCY register added in SYSCON block. See Table 35.
• Reset value of the C_CAN CANCLKDIV register changed to 0x1, See Table 275.
• RAM used by ISP sizes updated. See Section 26.4.8, Section 26.4.9.
• SSEL1_LOC Register description corrected. See Table 152.
• Added LPC1115FET48.
• Editorial updates.
• Updated Go command Section 26.5.8.
12 20120924 LPC111x/LPC11C1x/LPC11C2x User manual
Modifications:
• BOD level 0 for reset added. See Table 33.
• Description of the TEMT bit in the UART LSR register updated. See Table 196.
11 20120726 LPC111x/LPC11C1x/LPC11C2x User manual
Modifications:
• Function SSEL1 added to pin PIO2_0 in Table 170 and Figure 28.
• BOD level 0 for reset and interrupt removed.
10 20120626 LPC111x/LPC11C1x/LPC11C2x User manual
Modifications:
• LPC1112FHN24 pinout corrected in Table 161 and Figure 18.
• Description of BYPASS bit corrected in Table 12 “System oscillator control register (SYSOSCCTRL,
address 0x4004 8020) bit description”.
9 20120517 LPC111x/LPC11C1x/LPC11C2x/LPC11D14 User manual