Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 285 of 547
NXP Semiconductors
UM10398
Chapter 16: LPC111x/LPC11Cxx C_CAN controller
CANIF1_DA1 R/W 0x03C Message interface 1 data A1 0x0000
CANIF1_DA2 R/W 0x040 Message interface 1 data A2 0x0000
CANIF1_DB1 R/W 0x044 Message interface 1 data B1 0x0000
CANIF1_DB2 R/W 0x048 Message interface 1 data B2 0x0000
--0x04C -
0x07C
Reserved -
CANIF2_CMDREQ R/W 0x080 Message interface 2 command request 0x0001
CANIF2_CMDMSK_W R/W 0x084 Message interface 2 command mask (write
direction)
0x0000
CANIF2_CMDMSK_R R/W 0x084 Message interface 2 command mask (read
direction)
0x0000
CANIF2_MSK1 R/W 0x088 Message interface 2 mask 1 0xFFFF
CANIF2_MSK2 R/W 0x08C Message interface 2 mask 2 0xFFFF
CANIF2_ARB1 R/W 0x090 Message interface 2 arbitration 1 0x0000
CANIF2_ARB2 R/W 0x094 Message interface 2 arbitration 2 0x0000
CANIF2_MCTRL R/W 0x098 Message interface 2 message control 0x0000
CANIF2_DA1 R/W 0x09C Message interface 2 data A1 0x0000
CANIF2_DA2 R/W 0x0A0 Message interface 2 data A2 0x0000
CANIF2_DB1 R/W 0x0A4 Message interface 2 data B1 0x0000
CANIF2_DB2 R/W 0x0A8 Message interface 2 data B2 0x0000
--0x0AC -
0x0FC
Reserved -
CANTXREQ1 RO 0x100 Transmission request 1 0x0000
CANTXREQ2 RO 0x104 Transmission request 2 0x0000
- - 0x108 -
0x11C
Reserved -
CANND1 RO 0x120 New data 1 0x0000
CANND2 RO 0x124 New data 2 0x0000
- - 0x128 -
0x13C
Reserved -
CANIR1 RO 0x140 Interrupt pending 1 0x0000
CANIR2 RO 0x144 Interrupt pending 2 0x0000
- - 0x148 -
0x15C
Reserved -
CANMSGV1 RO 0x160 Message valid 1 0x0000
CANMSGV2 RO 0x164 Message valid 2 0x0000
- - 0x168 -
0x17C
Reserved -
CANCLKDIV R/W 0x180 Can clock divider register 0x0001
Table 245. Register overview: CCAN (base address 0x4005 0000)
Name Access Address
offset
Description Reset
value