Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 310 of 547
NXP Semiconductors
UM10398
Chapter 16: LPC111x/LPC11Cxx C_CAN controller
16.7.3.1 Management of message objects
The configuration of the Message Objects in the Message RAM will (with the exception of
the bits MSGVAL, NEWDAT, INTPND, and TXRQST) is not be affected by resetting the
chip. All the Message Objects must be initialized by the CPU or they must be set to not
valid (MSGVAL = ‘0’).The bit timing must be configured before the CPU clears the INIT bit
in the CAN Control Register.
The configuration of a Message Object is done by programming Mask, Arbitration, Control
and Data field of one of the two interface register sets to the desired values. By writing to
the corresponding IFx Command Request Register, the IFx Message Buffer Registers are
loaded into the addressed Message Object in the Message RAM.
When the INIT bit in the CAN Control Register is cleared, the CAN Protocol Controller
state machine of the CAN core and the Message Handler State Machine control the CAN
controller’s internal data flow. Received messages that pass the acceptance filtering are
stored into the Message RAM, and messages with pending transmission request are
loaded into the CAN core’s shift register and are transmitted via the CAN bus.
The CPU reads received messages and updates messages to be transmitted via the IFx
Interface Registers. Depending on the configuration, the CPU is interrupted on certain
CAN message and CAN error events.
Fig 65. Block diagram of a message object transfer
IF1 MASK1, 2
IF1 ARBITRATION 1/2
IF1 MESSAGE CTRL
IF1 DATA A1/2
IF1 DATA B1/2
IF2 MASK1, 2
IF2 ARBITRATION 1/2
IF2 MESSAGE CTRL
IF2 DATA A1/2
IF2 DATA B1/2
MESSAGE RAM
MESSAGE OBJECT 1
MESSAGE OBJECT 2
.
.
.
MESSAGE OBJECT 32
transfer a
message object
read transfer
write transfer
APB
bus
MESSAGE BUFFER
REGISTERS
IF1 COMMAND REQUEST
IF1 COMMAND MASK
IF2 COMMAND REQUEST
IF2 COMMAND MASK
INTERFACE
COMMAND REGISTERS
MESSAGE HANDLER
TRANSMISSION REQUEST 1/2
NEW DATA 1/2
INTERRUPT PENDING1/2
MESSAGE VALID1/2
CAN
bus
receive
transfer a
CAN frame
transmit
CAN CORE/
SHIFT REGISTERS