Datasheet
UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 377 of 547
NXP Semiconductors
UM10398
Chapter 21: LPC1100XL series: 32-bit counter/timer CT32B0/1
21.4 Applications
• Interval timer for counting internal events
• Pulse Width Demodulator via capture input
• Free running timer
• Pulse Width Modulator via match outputs
21.5 Description
Each Counter/timer is designed to count cycles of the peripheral clock (PCLK) or an
externally supplied clock and can optionally generate interrupts or perform other actions at
specified timer values based on four match registers. The peripheral clock is provided by
the system clock (see Figure 8
). Each counter/timer also includes one capture input to
trap the timer value when an input signal transitions, optionally generating an interrupt.
In PWM mode, three match registers can be used to provide a single-edge controlled
PWM output on the match output pins. One match register is used to control the PWM
cycle length.
Remark: 32-bit counter/timer0 (CT32B0) and 32-bit counter/timer1 (CT32B1) are
functionally identical except for the peripheral base address.
21.6 Pin description
Table 327 gives a brief summary of each of the counter/timer related pins.
21.7 Register description
32-bit counter/timer0 contains the registers shown in Table 328 and 32-bit counter/timer1
contains the registers shown in Table 329
. More detailed descriptions follow.
Table 327. Counter/timer pin description
Pin Type Description
CT32B0_CAP[1:0]
CT32B1_CAP[1:0]
Input Capture Signals:
A transition on a capture pin can be configured to load one of the Capture Registers
with the value in the Timer Counter and optionally generate an interrupt.
The counter/timer block can select a capture signal as a clock source instead of the
PCLK derived clock. For more details see Section 21.7.11 “
Count Control Register
(TMR32B0CTCR and TMR32B1TCR)” on page 386.
CT32B0_MAT[3:0]
CT32B1_MAT[3:0]
Output External Match Output of CT32B0/1:
When a match register TMR32B0/1MR3:0 equals the timer counter (TC), this output
can either toggle, go LOW, go HIGH, or do nothing. The External Match Register
(EMR) and the PWM Control register (PWMCON) control the functionality of this
output.