Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 454 of 547
NXP Semiconductors
UM10398
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
The Cortex-M0 processor is built on a highly area and power optimized 32-bit processor
core, with a 3-stage pipeline von Neumann architecture. The processor delivers
exceptional energy efficiency through a small but powerful instruction set and extensively
optimized design, providing high-end processing hardware including a single-cycle
multiplier.
The Cortex-M0 processor implements the ARMv6-M architecture, which is based on the
16-bit Thumb instruction set and includes Thumb-2 technology. This provides the
exceptional performance expected of a modern 32-bit architecture, with a higher code
density than other 8-bit and 16-bit microcontrollers.
The Cortex-M0 processor closely integrates a configurable Nested Vectored Interrupt
Controller (NVIC), to deliver industry-leading interrupt performance. The NVIC:
• includes a non-maskable interrupt (NMI). See Section 28.1 for implementation of
the NMI for specific parts.
• provides zero jitter interrupt option
• provides four interrupt priority levels.
The tight integration of the processor core and NVIC provides fast execution of interrupt
service routines (ISRs), dramatically reducing the interrupt latency. This is achieved
through the hardware stacking of registers, and the ability to abandon and restart
load-multiple and store-multiple operations. Interrupt handlers do not require any
assembler wrapper code, removing any code overhead from the ISRs. Tail-chaining
optimization also significantly reduces the overhead when switching from one ISR to
another.
To optimize low-power designs, the NVIC integrates with the sleep modes, that include a
Deep-sleep function that enables the entire device to be rapidly powered down.
28.3.1 System-level interface
The Cortex-M0 processor provides a single system-level interface using AMBA
technology to provide high speed, low latency memory accesses.
28.3.2 Integrated configurable debug
The Cortex-M0 processor implements a complete hardware debug solution, with
extensive hardware breakpoint and watchpoint options. This provides high system
visibility of the processor, memory and peripherals through a 2-pin Serial Wire Debug
(SWD) port that is ideal for microcontrollers and other small package devices.
28.3.3 Cortex-M0 processor features summary
• high code density with 32-bit performance
• tools and binary upwards compatible with Cortex-M processor family
• integrated ultra low-power sleep modes
• efficient code execution permits slower processor clock or increases sleep mode time
• single-cycle 32-bit hardware multiplier
• zero jitter interrupt handling